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A49LF004 Datasheet(PDF) 5 Page - AMIC Technology

Part No. A49LF004
Description  4 Mbit CMOS 3.3Volt-only Firmware Hub Flash Memory
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Maker  AMICC [AMIC Technology]
Homepage  http://www.amictechnology.com
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A49LF004 Datasheet(HTML) 5 Page - AMIC Technology

 
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A49LF004
PRELIMINARY
(November, 2003, Version 0.0)
4
AMIC Technology, Corp.
Table 1: Pin Description
1. IN=Input, OUT=output, I/O=Input/Output, PWR=Power
Interface
Symbol
Pin Name
Type
A/A
Mux
FWH
Descriptions
A10-A0
Address
IN
X
Inputs for addresses during Read and Write operations in A/A
Mux mode. Row and column addresses are latched by R/C# pin.
I/O7-I/O0
Data
I/O
X
To output data during Read cycle and receive input data during
Write cycle in A/A Mux mode. The outputs are in tri-state when
OE# is high.
OE#
Output Enable
IN
X
To control the data output buffers.
WE#
Write Enable
IN
X
To control the Write operations.
IC
Interface
Configuration Pin
IN
X
X
To determine which interface is operational. When held high, A/A
Mux mode is enabled and when held low, FWH mode is enabled.
This pin must be setup at power-up or before return from reset
and not change during device operation. This pin is internally
pulled down with a resistor between 20-100 K
Ω.
INIT#
Initialize
IN
X
This is the second reset pin for in-system use. INIT# and RST#
pins are internally combined and initialize a device reset when
driven low.
ID[3:0]
Identification Inputs
IN
X
These four pins are part of the mechanism that allows multiple
FWH devices to be attached to the same bus. To identify the
component, the correct strapping of these pins must be set. The
boot device must have ID[3:0]=0000 and it is recommended that
all subsequent devices should use sequential up-count
strapping. These pins are internally pulled down with a resistor
between 20-100 K
Ω.
FGPI[4:0]
General Purpose
Inputs
IN
X
These individual inputs can be used for additional board
flexibility. The state of these pins can be read immediately at
boot, through FWH internal registers. These inputs should be at
their desired state before the start of the PCI clock cycle during
which the read is attempted, and should remain in place until the
end of the Read cycle. Unused FGPI pins must not be floated.
TBL#
Top Block Lock
IN
X
To prevent any write operations to the Boot Block when driven
low, regardless of the state of the block lock registers. When
TBL# is high it disables hardware write protection for the top
Boot Block. This pin cannot be left unconnected.
FWH[3:0]
FWH I/Os
I/O
X
I/O Communications in FWH mode.
CLK
Clock
IN
X
To provide a clock input to the device. This pin is the same as
that for the PCI clock and adheres to the PCI specifications.
FWH4
FWH Input
IN
X
Input communication in FWH mode.
RST#
Reset
IN
X
X
To reset the operation of the device
WP#
Write Protect
IN
X
When low, prevents any write operations to all but the highest
addressable block. When WP# is high it disables hardware write
protection for these blocks. This pin cannot be left unconnected.
R/C#
Row/Column Select
IN
X
This pin determines whether the address pins are pointing to the
row addresses or the column addresses in A/A Mux mode.
RB#
Ready/Busy#
OUT
X
To determine if the device is busy in write operations. Valid only
in A/A Mux mode.
RES
Reserved
X
Reserved. These pins must be left unconnected.
VDD
Power Supply
PWR
X
X
To provide power supply (3.0-3.6Volt).
VSS
Ground
PWR
X
X
Circuit ground. All VSS pins must be grounded.
NC
No Connection
X
X
Unconnected pins.


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