Avago Technologies

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ACPL-K33T

Data Sheet

Thermal Resistance Model for ACPL-K33T

Measurement is done on both low and high conductivity boards as shown in the following table.

NOTE

These thermal resistances R11, R12, R21 and R22 can be improved by increasing the ground plane/copper area.

Application and environment design for ACPL-K33T needs to ensure that the junction temperature of the internal IC and LED

within the gate drive optocoupler do not exceed 150 °C. Use equation (1) and equation (2) to estimate the junction temperatures.

For example:

Calculation of LED and output IC power dissipation:

= 13 mA × 1.25 V × 50%

= 8.125 mW

= 30 V × 4.2 mA + 60 mW + 34.3 mW

= 220.3 mW

where

Layout

Measurement Data

Low conductivity board per JEDEC 51-3:

R11 = 191 °C/W

R12 = R21 = 68.5 °C/Wx

22 = 77 °C/W

High conductivity board per JEDEC 51-7:

R11 = 155 °C/W

R12 = R21 = 64 °C/W

R22=41 °C/W

= High side switching power dissipation

= (30 V × 80 nC × 200 kHz) × 4

/(4 +12 )/2

= 60 mW

= Low side switching power dissipation

= (VCC × QG × fPWM) × RDS,OL(MAX)/(RDS,OL(MAX) + RGL)/2

= (30 V × 80 nC × 200 kHz) × 2

/(2 +12 )/2

= 34.3 mW

= Gate charge at supply voltage

= LED switching frequency

= Gate charging resistance

= Gate discharging resistance

76.2 mm