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ZL30105 Datasheet(PDF) 30 Page - Zarlink Semiconductor Inc |
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ZL30105 Datasheet(HTML) 30 Page - Zarlink Semiconductor Inc |
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30 / 50 page  ZL30105 Data Sheet 30 Zarlink Semiconductor Inc. 4.7 Pull-in Range Also referred to as capture range. This is the input frequency range over which the PLL must be able to pull into synchronization. 4.8 Lock Range This is the input frequency range over which the synchronizer must be able to maintain synchronization. 4.9 Phase Slope Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. Another way of specifying the phase slope is as the fractional change per time unit. For example; a phase slope of 61 µs/s can also be specified as 61 ppm. 4.10 Time Interval Error (TIE) TIE is the time delay between a given timing signal and an ideal timing signal. 4.11 Maximum Time Interval Error (MTIE) MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. 4.12 Phase Continuity Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the PLL after a signal disturbance due to a reference switch or a mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. 4.13 Lock Time This is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter). Lock time is affected by many factors which include: • initial input to output phase difference • initial input to output frequency difference • PLL loop filter bandwidth • PLL phase slope limiter • in-lock phase distance The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and frequency. Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. |
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