SC68C752B datasheet(24/49 Pages) PHILIPS

Part #	SC68C752B

Description	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and Motorola uP interface

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Manufacturer	PHILIPS [NXP Semiconductors]

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SC68C752B_3

Product data sheet

Rev. 03 — 29 November 2005

24 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.4 Line Control Register (LCR)

This register controls the data communication format. The word length, number of stop

bits, and parity type are selected by writing the appropriate bits to the LCR. Table 13

shows the Line Control Register bit settings.

Table 13:

Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6

LCR[6]

Break control bit. When enabled, the Break control bit causes a break

condition to be transmitted (the TX output is forced to a logic 0 state). This

condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 to alert the

communication terminal to a line break condition

5

LCR[5]

Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).

logic 0 = parity is not forced (normal default condition)

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1 for

the transmit and receive data.

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0 for

the transmit and receive data.

4

LCR[4]

Parity type select.

logic 0 = odd parity is generated (if LCR[3] = 1).

logic 1 = even parity is generated (if LCR[3] = 1).

3

LCR[3]

Parity enable.

logic 0 = no parity (normal default condition).

logic 1 = a parity bit is generated during transmission and the receiver

checks for received parity.

2

LCR[2]

Number of stop bits. Speciﬁes the number of stop bits.

0 = 1 stop bit (word length = 5, 6, 7, 8)

1 = 1.5 stop bits (word length = 5)

1 = 2 stop bits (word length = 6, 7, 8)

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received.

00 = 5 bits

01 = 6 bits

10 = 7 bits

11 = 8 bits

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