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PC8260VTPU150 Datasheet(PDF) 32 Page - ATMEL Corporation |
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PC8260VTPU150 Datasheet(HTML) 32 Page - ATMEL Corporation |
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32 / 53 page  32 PC8260 PowerQUICC II 2131B–HIREL–02/03 MODCK3 AP[3] TC[2] BNKSEL[2] Clock Mode Input I Defines the operating mode of internal clock circuits. Address Parity 3 I/O The 60x master that drives the address bus, also drives the address parity signals. The value driven on the address parity 3 pin should provide odd parity (odd number of 1’s) on the group of signals that includes address parity 3and [A24:314]. Transfer Code 2 O The transfer code output pins supply information that can be useful for debug purposes for each of the PowerQUICC II initiated bus transactions. Bank Select 2 O The bank select outputs are used for selecting SDRAM bank when the PowerQUICC II is in 60x compatible bus mode. XFC External Filter Capacitance I Input connection for an external capacitor filter for PLL circuity. CLKIN Clock In I Primary clock input to PowerQUICC II’s PLL. PA[0:31] Port A Bits 0:31 I/O General Purpose I/O Port PB[4:31] Port B Bits 4:31 I/O General Purpose I/O Port PC[0:31] Port C Bits 0:31 I/O General Purpose I/O Port PD[4:31] Port D Bits 4:31 I/O General Purpose I/O Port VDD VDDH VCCSYN GNDSYN VCCSYN1 Power Supply Power Supply Power Supply Special Ground Power Supply Power supply of the internal logic Power supply of the I/O buffers Power supply of the PLL circuity Special ground of the PLL circuity Power supply of the core’s PLL circuity Table 4. External Signals (Continued) Pin Signal Name Type Description |
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