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PC87383 Datasheet(PDF) 31 Page - National Semiconductor (TI) |
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PC87383 Datasheet(HTML) 31 Page - National Semiconductor (TI) |
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31 / 77 page  3.0 Device Architecture and Configuration (Continued) Revision 1.1 31 www.national.com 3.7.6 Clock Generator Control Register (CLOCKCF) Location: Index 29h Type: Varies per bit Bit 76 5 43210 Name CKEN Reserved CK48SEL CKVALID LOCKCCF Reserved Reset 0 0 0 00000 Bit Type Description 7 R/W or RO CKEN (Clock Enable). This bit enables the internal clock of PC87383. If the clock source selected by CK48SEL bit is the Clock Generator, this bit enables the Clock Generator. Otherwise it enables the path from the CLKIN input pin. 0: Clock disabled (default). 1: Clock enabled. 6 Reserved. 5 R/W or RO CK48SEL (48 MHz Clock Select). Selects the source of the internal 48 MHz clock. 0: The source of the internal 48 MHz clock is CLKIN pin (default). Use when CLKIN pin is connected to 48 MHz clock source. 1: The source of the internal 48 MHz clock is the Clock Generator. Use when CLKIN pin is connected to 14.31818 MHz clock source. 4RO CKVALID (Valid Clock Generator, Clock Status). This bit indicates the status of the on-chip, 48 MHz Clock Generator and controls the generator output clock signal. The PC87383 modules using this clock may be enabled (see Section 3.3.1 on page 25) only after this bit is read high (generator clock is valid). 0: Generator output clock frozen (default). 1: Generator output clock active (stable and toggling). 3 R/W1S LOCKCCF (Lock Clock Configuration). When set to 1, this bit locks the configuration register CLOCKCF by disabling writing to all its bits (including to the LOCKCCF bit itself). Once set, this bit can be cleared by Hardware reset. 0: The R/W bits are enabled for write (default). 1: All the bits are Read-Only. 2-0 Reserved. |
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