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ARM-610 Datasheet(PDF) 79 Page - Zarlink Semiconductor Inc |
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ARM-610 Datasheet(HTML) 79 Page - Zarlink Semiconductor Inc |
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79 / 173 page  Instruction Set - LDC, STC ARM610 Data Sheet 4-51 4.13.7 Assembler syntax <LDC|STC>{cond}{L} p#,cd,<Address> LDC load from memory to coprocessor STC store from coprocessor to memory {L} when present perform long transfer (N=1), otherwise perform short transfer (N=0) {cond} two character condition mnemonic. See · Table 4-2: Condition code summary on page 4-6. p# the unique number of the required coprocessor cd is an expression evaluating to a valid coprocessor register number that is placed in the CRd field <Address> can be: 1 An expression which generates an address: <expression> The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression. This will be a PC relative, pre-indexed address. If the address is out of range, an error will be generated. 2 A pre-indexed addressing specification: [Rn] offset of zero [Rn,<#expression>]{!} offset of <expression> bytes 3 A post-indexed addressing specification: [Rn],<#expression> offset of <expression> bytes {!} write back the base register (set the W bit) if! is present Rn is an expression evaluating to a valid ARM610 register number. Note If Rn is R15, the assembler will subtract 8 from the offset value to allow for ARM610 pipelining. |
Similar Part No. - ARM-610 |
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