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ARM610 Datasheet(PDF) 39 Page - Zarlink Semiconductor Inc |
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ARM610 Datasheet(HTML) 39 Page - Zarlink Semiconductor Inc |
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39 / 173 page  Instruction Set - Shifts ARM610 Data Sheet 4-11 Arithmetic operations The arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN) treat each operand as a 32-bit integer (either unsigned or two's complement signed, the two are equivalent). If the S bit is set (and Rd is not R15) the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were considered unsigned, but warns of a possible error if the operands were two's complement signed. The C flag will be set to the carry out of bit 31 of the ALU, the Z flag will be set if and only if the result was zero, and the N flag will be set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be two's complement signed). 4.4.2 Shifts When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the Shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). The amount by which the register should be shifted may be contained in an immediate field in the instruction, or in the bottom byte of another register (other than R15). The encoding for the different shift types is shown in · Figure 4-4: ARM shift operations. Figure 4-4: ARM shift operations MOV 1101 operand2 (operand1 is ignored) BIC 1110 operand1 AND NOT operand2 (Bit clear) MVN 1111 NOT operand2 (operand1 is ignored) Assembler Mnemonic OpCode Action Table 4-3: ARM Data processing instructions 11 7654 0 11 87654 Rs 0 1 Shift type 00= logical left 01= logical right 10= arithmetic right 11= rotate right Shift amount 5-bit unsigned integer Shift type 00= logical left 01= logical right 10= arithmetic right 11= rotate right Shift amount shift amount specified in bottom byte of Rs |
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