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P89LPC907 Datasheet(PDF) 39 Page - NXP Semiconductors |
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P89LPC907 Datasheet(HTML) 39 Page - NXP Semiconductors |
39 / 51 page Philips Semiconductors P89LPC906/907/908 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 05 — 17 December 2004 39 of 51 9397 750 14467 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. may be used to wake up the CPU from Idle or Power down modes. This feature is particularly useful in handheld, battery powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than 6 CCLKs. 8.23 Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the Watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 17 shows the watchdog timer in Watchdog mode. Feeding the Watchdog requires a two-byte sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from afew µs to a few seconds. Please refer to the P89LPC906/907/908 User’s Manual for more details. 8.24 Additional features 8.24.1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or Watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets. (1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence. Fig 17. Watchdog timer in Watchdog mode (WDTE = ‘1’). PRE2 PRE1 PRE0 – – WDRUN WDTOF WDCLK WDCON (A7H) CONTROL REGISTER PRESCALER 002aaa423 SHADOW REGISTER FOR WDCON 8-BIT DOWN COUNTER WDL (C1H) Watchdog oscillator PCLK ÷32 MOV WFEED1, #0A5H MOV WFEED2, #05AH RESET see note (1) |
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