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NBSG53A Datasheet(PDF) 4 Page - ON Semiconductor

Part No. NBSG53A
Description  2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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NBSG53A Datasheet(HTML) 4 Page - ON Semiconductor

 
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NBSG53A
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Table 5. ATTRIBUTES
Characteristics
Value
Positive Operating Voltage Range for VCC (VEE = 0 V)
2.375 V to 3.465 V
Negative Operating Voltage Range for VEE (VCC = 0 V)
−2.375 V to −3.465 V
Internal Input Pulldown Resistor (R, SEL)
75 k
W
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 50 V
> 4 kV
Moisture Sensitivity (Note 5)
16−FCBGA
16−QFN
Level 3
Level 1
Flammability Rating
UL 94 V−0 @ 0.125 in
Oxygen Index
28 to 34
Transistor Count
482
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
5. For additional information, refer to Application Note AND8003/D.
Table 6. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
Positive Power Supply
VEE = 0 V
3.6
V
VEE
Negative Power Supply
VCC = 0 V
−3.6
V
VI
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
VI v VCC
VI w VEE
3.6
−3.6
V
V
VINPP
Differential Input Voltage
|D − D|
VCC − VEE w 2.8 V
VCC − VEE <
2.8 V
2.8
|VCC − VEE|
V
V
IIN
Input Current Through RT (50 W Resistor)
Static
Surge
45
80
mA
mA
IOUT
Output Current
Continuous
Surge
25
50
mA
mA
TA
Operating Temperature Range
16 FCBGA
16 QFN
−40 to +70
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 6)
0 LFPM
500 LFPM
0 LFPM
500 LFPM
16 FCBGA
16 FCBGA
16 QFN
16 QFN
108
86
41.6
35.2
°C/W
°C/W
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P (Note 6)
2S2P (Note 7)
16 FCBGA
16 QFN
5.0
4.0
°C/W
°C/W
Tsol
Wave Solder
< 15 Seconds
225
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
6. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
7. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.


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