MPC9330

MOTOROLA

TIMING SOLUTIONS

2

Figure 1. MPC9330 Logic Diagram

GND

QA1

QA0

VCC

FSELA

FSELB

FSELC

GND

QC1

QC0

VCC

FB_IN

CLK_STOP1

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

123456

78

24

23

22

21

20

19

18

17

16

MPC9330

Figure 2. MPC9330 32–Lead Package Pinout (Top View)

NC

The MPC9330 requires an external RC filter for the analog power supply pin VCC_PLL. Please see application section for details.

CLK_STOP0

NC

PLL

÷2

÷4

÷6

1

0

0

1

÷16

1

0

1

0

÷2

÷4

1

0

1

0

1

0

3

OE/MR

QA0

QA1

QB0

QB1

QC0

QC1

Bank A

Bank B

Bank C

25k

25k

3 x 25k

25k

VCC

VCC

25k

VCC

25k

VCC

3 x 25k

VCC

CLK

STOP

CLK

STOP

CLK

STOP

Ref

FB

VCO

CLK_STOP1

CLK_STOP0

FSELC

FSELB

FSELA

PLL_EN

PWR_DN

FB_SEL

FB_IN

REF_SEL

CCLK

XTAL_OUT

XTAL_IN

XTAL

25k