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M34F04 Datasheet(PDF) 5 Page - STMicroelectronics

Part No. M34F04
Description  4Kbit Serial I2C Bus EEPROM With Hardware Write Control on Top Half of Memory
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M34F04 Datasheet(HTML) 5 Page - STMicroelectronics

 
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M34F04
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to
strobe all data in and out of the device. In applica-
tions where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor can be connected from Serial
Clock (SCL) to VCC. (Figure 4 indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the bus master
has a push-pull (rather than open drain) output.
Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR’ed with
other open drain or open collector signals on the
bus. A pull up resistor must be connected from Se-
rial Data (SDA) to VCC. (Figure 4 indicates how the
value of the pull-up resistor can be calculated).
Chip Enable (E1, E2). These input signals are
used to set the value that is to be looked for on the
three least significant bits (b3, b2) of the 7-bit De-
vice Select Code. These inputs must be tied to
VCC or VSS, to establish the Device Select Code.
Write Control (WC). This input signal is useful
for protecting half of the memory from inadvertent
write operations. Write operations are disabled to
the upper half (1FFh to 100h) of the memory array
when Write Control (WC) is driven High. When un-
connected, the signal is internally read as VIL, and
Write operations are allowed.
When attempting to write in the upper half of the
memory, while Write Control (WC) is being driven
High, Device Select and Address bytes are ac-
knowledged, Data bytes are not acknowledged.
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I
2C Bus
AI01665
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
0
4
8
12
16
20
CBUS (pF)
10
1000
fc = 400kHz
fc = 100kHz


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