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LUPA-4000
Data Sheet
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: info@Fillfactory.com
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 11 of 49
3 Sensor architecture
A schematic drawing of the architecture is given in the block diagram below. The
image core consists of a pixel array, one X- and two Y-addressing registers (only one
drawn), pixel array drivers and column amplifiers. The image sensor of 2048 * 2048
pixels is read out in progressive scan. One or two output amplifiers read out the
image sensor. The output amplifiers are working at 66MHz pixel rate nominal speed
or each at 33MHz pixel rate in case the 2 output amplifiers are used to read out the
imager. The complete image sensor has been designed for operation up to 66MHz.
The structure allows having a programmable addressing in the x-direction in steps of
2 and in the y-direction in steps of 2 (only even start addresses in X- and Y-direction
are possible). The starting point of the address is uploadable by means of the Serial-
Parallel Interface (SPI).
Column amplifiers
On chip drivers
eos_y
Clk_y sync_y
2 differentia
outputs
eos_x
Reset, mem_hl,
precharge, samp
pixel array
2048 * 2048
X shift register
sync_x
Clk_x
Logic blocks
DAC
SPI
Figure 3: Block diagram of the image sensor
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