K4D551638D-TC2A datasheet(10/18 Pages) SAMSUNG

Part #	K4D551638D-TC2A

Description	256Mbit GDDR SDRAM

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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10 / 18 page

256M GDDR SDRAM

K4D551638D-TC

- 10 -

Rev 1.8 (Oct. 2003)

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65

°C)

Parameter

Symbol

Min

Typ

Max

Unit

Note

Device Supply voltage

VDD

2.5

2.6

2.7

V

1,7,8

Output Supply voltage

VDDQ

2.5

2.6

2.7

V

1,7,8

Reference voltage

VREF

0.49*VDDQ

-

0.51*VDDQ

V2

Termination voltage

Vtt

VREF-0.04

VREF

VREF+0.04

V

3

Input logic high voltage

VIH(DC)

VREF+0.15

-

VDDQ+0.30

V

4

Input logic low voltage

VIL(DC)

-0.30

-

VREF-0.15

V

5

Output logic high voltage

VOH

Vtt+0.76

-

V

IOH=-15.2mA

Output logic low voltage

VOL

-

Vtt-0.76

V

IOL=+15.2mA

Input leakage current

IIL

-5

-

5

uA

6

Output leakage current

IOL

-5

-

5

uA

6

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

VIN, VOUT

-0.5 ~ 3.6

V

Voltage on VDD supply relative to Vss

VDD

-1.0 ~ 3.6

V

Voltage on VDD supply relative to Vss

VDDQ

-0.5 ~ 3.6

V

Storage temperature

TSTG

-55 ~ +150

°C

Power dissipation

PD

2.0

W

Short circuit current

IOS

50

mA

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to

peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error

and an additional + 25mV for AC noise.

3. Vtt of the transmitting device must track VREF of the receiving device.

4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.

7. For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V.

8. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%.

Note :

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