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IDT72V2113L15BCI Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT72V2113L15BCI Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 46 page  4 IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Emptyflag)and PAF(ProgrammableAlmost-Fullflag).TheEFandFF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode. PAE and PAFcanbeprogrammedindependentlytoswitchatanypointin memory.Programmableoffsetsdeterminetheflagswitchingthresholdandcan beloadedbytwomethods:parallelorserial.Eightdefaultoffsetsettingsarealso provided, so that PAEcanbesettoswitchatapredefinednumberoflocations from the empty boundary and the PAF threshold can also be set at similar predefinedvaluesfromthefullboundary.Thedefaultoffsetvaluesaresetduring Master Reset by the state of the FSEL0, FSEL1, and LD pins. Forserialprogramming, SENtogetherwithLDoneachrisingedgeofWCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WENtogetherwith LD oneachrisingedgeofWCLK,areused to load the offset registers via Dn. REN together with LD on each rising edge ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether serial or parallel offset loading has been selected. During Master Reset ( MRS)thefollowingeventsoccur:thereadandwrite pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset ( PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation, when reprogramming programmable flags would be undesirable. Itisalsopossibletoselectthetimingmodeofthe PAE(ProgrammableAlmost- Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAEand PAFflags. If asynchronous PAE/PAF configuration is selected, the PAEis asserted LOWontheLOW-to-HIGHtransitionofRCLK. PAEisresettoHIGHontheLOW- DESCRIPTION (CONTINUED) (x9 or x18) DATA OUT (Q0 - Qn) (x9 or x18) DATA IN (D0 - Dn) MASTER RESET ( MRS) READ CLOCK (RCLK/RD*) READ ENABLE ( REN) OUTPUT ENABLE ( OE) EMPTY FLAG/OUTPUT READY ( EF/OR) PROGRAMMABLE ALMOST-EMPTY ( PAE) WRITE CLOCK (WCLK/WR*) WRITE ENABLE ( WEN) LOAD ( LD) FULL FLAG/INPUT READY ( FF/IR) PROGRAMMABLE ALMOST-FULL ( PAF) IDT 72V2103 72V2113 PARTIAL RESET ( PRS) FIRST WORD FALL THROUGH/SERIAL INPUT (FWFT/SI) RETRANSMIT ( RT) 6119 drw03 HALF-FULL FLAG ( HF) SERIAL ENABLE( SEN) INPUT WIDTH (IW) OUTPUT WIDTH (OW) BIG-ENDIAN/LITTLE-ENDIAN ( BE) INTERSPERSED/ NON-INTERSPERSED PARITY (IP) SERIAL CLOCK (SCLK) Figure 1. Single Device Configuration Signal Flow Diagram |
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