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EN29F08090TI Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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EN29F08090TI Datasheet(HTML) 8 Page - List of Unclassifed Manufacturers |
8 / 37 page 4800 Great America Parkway, Suite 202 Tel: 408-235-8680 Santa Clara, CA 95054 Fax: 408-235-8685 8 EN29F080 Rev. C, Issue Date: 2001/07/05 Hardware Data protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise. Low VCC Write Inhibit When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than VLKO. Write Pulse “Glitch” protection Noise pulses of less than 5 ns (typical) on OE , CE or WE do not initiate a write cycle. Logical Inhibit If CE =VIH or WE=VIH, writing is inhibited. To initiate a write cycle, CE and WE must be a logical “zero”. If CE , WE , and OE are all logical zero (not recommended usage), it will be considered a write. Power-up Write Inhibit During power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE = VIL, WE = VIL and OE = VIH, the device will not accept commands on the rising edge of WE . |
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