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DS1249W Datasheet(PDF) 2 Page - Dallas Semiconductor

Part No. DS1249W
Description  3.3V 2048kb Nonvolatile SRAM
Download  8 Pages
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Maker  DALLAS [Dallas Semiconductor]
Homepage  http://www.dalsemi.com
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DS1249W Datasheet(HTML) 2 Page - Dallas Semiconductor

   
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DS1249W
2 of 8
READ MODE
The DS1249 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 18 address inputs
(A0 – A17) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight
data output drivers within tACC (Access Time) after the last address input signal is stable, providing that
CE
and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either tCO for
CE
or tOE for OE rather than tACC.
WRITE MODE
The DS1249 executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active), then WE
will disable the outputs in tODW from its falling edge.
DATA-RETENTION MODE
The DS1249W provides full functional capability for VCC greater than 3.0 volts and write protects by
2.8V. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
write protects themselves, all inputs become “don’t care,” and all outputs become high impedance. As
VCC falls below approximately 2.5V, a power-switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5V, the power-switching
circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM
operation can resume after VCC exceeds 3.0V.
FRESHNESS SEAL
Each DS1249 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium
energy source is enabled for battery backup operation.


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