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DS1249W Datasheet(PDF) 6 Page - Dallas Semiconductor

Part No. DS1249W
Description  3.3V 2048kb Nonvolatile SRAM
Download  8 Pages
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Maker  DALLAS [Dallas Semiconductor]
Homepage  http://www.dalsemi.com
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DS1249W Datasheet(HTML) 6 Page - Dallas Semiconductor

   
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DS1249W
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POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
(TA: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
VCC Fail Detect to CE and WE Inactive
tPD
1.5
ms
11
VCC Slew from VTP to 0V
tF
150
ms
VCC Slew from 0V to VTP
tR
150
ms
VCC Valid to CE and WE Inactive
tPU
2ms
VCC Valid to End of Write Protection
tREC
125
ms
(TA = +25
°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Expected Data-Retention Time
tDR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition in Write
Cycle 1, the output buffers remain in a high-impedance state during this period.


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