CYP15G0201DXB
CYV15G0201DXB
Document #: 38-02058 Rev. *G
Page 2 of 46
The two channels may be combined to allow transport of wide
buses across significant distances with minimal concern for
offsets in clock phase or link delay. Each transmit channel
accepts parallel characters in an Input Register, encodes each
character for transport, and converts it to serial data. Each
receive channel accepts serial data and converts it to parallel
data, decodes the data into characters, and presents these
characters to an Output Register. Figure 1 illustrates typical
connections between independent host systems and corre-
sponding CYP(V)15G0201DXB parts. As a second-gener-
ation HOTLink device, the CYP(V)15G0201DXB extends the
HOTLink family with enhanced levels of integration and faster
data rates, while maintaining serial-link compatibility (data,
command, and BIST) with other HOTLink devices.
The transmit (TX) section of the CYP(V)15G0201DXB Dual
HOTLink II consists of two byte-wide channels that can be
operated independently or bonded to form wider buses. Each
channel
can
accept
either
8-bit
data
characters
or
pre-encoded 10-bit transmission characters. Data characters
are passed from the Transmit Input Register to an embedded
8B/10B Encoder to improve their serial transmission charac-
teristics. These encoded characters are then serialized and
output from dual Positive ECL (PECL) compatible differential
transmission-line drivers at a bit-rate of either 10 or 20 times
the input reference clock.
The receive (RX) section of the CYP(V)15G0201DXB Dual
HOTLink II consists of two byte-wide channels that can be
operated independently or synchronously bonded for greater
bandwidth. Each channel accepts a serial bit-stream from one
of two PECL-compatible differential line receivers and, using
a completely integrated PLL Clock Synchronizer, recovers the
timing information necessary for data reconstruction. Each
recovered
bit-stream
is
deserialized
and
framed
into
characters, 8B/10B decoded, and checked for transmission
errors. Recovered decoded characters are then written to an
internal Elasticity Buffer, and presented to the destination host
system. The integrated 8B/10B Encoder/Decoder may be
bypassed for systems that present externally encoded or
scrambled data at the parallel interface.
For those systems using buses wider than a single byte, the
two independent receive paths can be bonded together to
allow synchronous delivery of data across a two-byte-wide
(16-bit) path.
The parallel I/O interface may be configured for numerous
forms of clocking to provide the highest flexibility in system
architecture. In addition to clocking the transmit path interfaces
from one of multiple sources, the receive interface may be
configured to present data relative to a recovered clock or to a
local reference clock.
Each transmit and receive channel contains independent
Built-In Self-Test (BIST) pattern generators and checkers. This
BIST hardware allows at-speed testing of the high-speed
serial data paths in each transmit and receive section, and
across the interconnecting links.
HOTLink II devices are ideal for a variety of applications where
parallel
interfaces
can
be
replaced
with
high-speed,
point-to-point
serial
links.
Some
applications
include
interconnecting
backplanes
on
switches,
routers,
base-stations, servers and video transmission systems.
The CYV15G0201DXB is verified by testing to be compliant to
all the pathological test patterns, documented in SMPTE
EG34-1999 for both the SMPTE 259M and 292M signaling
rates. The tests ensure that the receiver recovers data with no
errors for the following patterns:
1. Repetitions of 20 ones and 20 zeros.
2. Single burst of 44 ones or 44 zeros.
3. Repetitions of 19 ones followed by 1 zero or 19 zeros
followed by 1 one.
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