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CY7B9945V-2AI Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY7B9945V-2AI
Description  High-speed Multi-phase PLL Clock Buffer
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7B9945V-2AI Datasheet(HTML) 4 Page - Cypress Semiconductor

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RoboClock
CY7B9945V
Document #: 38-07336 Rev. *D
Page 4 of 10
Output Disable Description
The output of each output bank can be independently put into
a HOLD-OFF or high-impedance state. The combination of the
MODE and DIS[1:2] inputs determines the clock outputs’ state
for each bank. When the DIS[1:2] is LOW, the outputs of the
corresponding banks will be enabled. When DIS[1:2] is HIGH,
the outputs for that bank will be disabled to a high-impedance
(HI-Z) or HOLD-OFF state. Table 5 defines the disabled
outputs functions.
The HOLD-OFF state is intended to be a power saving feature.
An output bank is disabled to the HOLD-OFF state in a
maximum of six output clock cycles from the time when the
disable input is HIGH. When disabled to the HOLD-OFF state,
outputs are driven to a logic LOW state on their falling edges.
This ensures the output clocks are stopped without a glitch.
When a bank of outputs is disabled to HI-Z state, the
respective bank of outputs will go HI-Z immediately.
Note:
3.
FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
FBInput
REFInput
–8tU
–7tU
–6tU
–4tU
–3tU
–2tU
–1tU
0t U
+1t U
+2t U
+3t U
LL
LM
LH
(N/A)
(N/A)
(N/A)
(N/A)
MM
(N/A)
(N/A)
(N/A)
(N/A)
HL
(N/A)
LL
LM
LH
ML
MH
MM
HM
HH
(N/A)
(N/A)
(N/A)
+4tU
+6t U
+7t U
+8t U
HM
HH
HL
(N/A)
(N/A)
2F[0:3]
1F[0:3]
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output[3]
Table 5. DIS[1:2] Functionality
MODE
DIS[1:2]
1Q[0:3], 2Q[0:5]
HIGH/LOW
LOW
ENABLED
HIGH
HIGH
HI-Z
LOW
HIGH
HOLD-OFF
MID
X
FACTORY TEST


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