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A8259 Datasheet(PDF) 7 Page - Altera Corporation |
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A8259 Datasheet(HTML) 7 Page - Altera Corporation |
7 / 24 page Altera Corporation 63 a8259 Programmable Interrupt Controller Data Sheet ICW 2 ICW 2 is selected after the a0 signal has been high. Input data for ICW 2 is sent via the din[7..0] bus, and data is clocked by the rising edge of clk . ICW 2 is deselected with the next falling edge of the nwr signal. Table 4 describes the ICW 2 register format. If SINGLE (bit 1 of ICW 1) is low, ICW 3 is the next register selected (see “ICW 3” on page 64). If SINGLE is high, ICW 3 is skipped. The next register considered is ICW 4 (see Figure 3 on page 61). If bit 0 of ICW 1 is high, then ICW 4 is the next register selected; if it is low, ICW 4 is skipped. When a write transaction is completed for ICW 4—or if it is skipped—the initialization sequence is finished, and the a8259 is now ready to accept interrupts. Table 3. ICW 1 Register Format (Part 2 of 2) Bit Mnemonic Description 3 LTIM Level-sensitive or edge-triggered input mode. When high, the ir[7..0] pins are level-sensitive inputs; otherwise, they are positive-edge-triggered. 4 1 This bit is used in conjunction with the a0 signal to select other command registers (see “Interrupt Registers” on page 69). 5 A5 These bits set the interrupt vector address (bits 5 through 7) in a 3-byte interrupt sequence (see “Interrupt Sequencing” on page 70). 6 A6 7 A7 Table 4. ICW 2 Register Format Bit Mnemonic Description 0 A8 These bits set the interrupt vector address. For bits 8 through 15, the interrupt vector address is set in a single- byte interrupt sequence mode. For bits 3 through 7, the interrupt vector address is set in the same mode. See “Operating Modes & Sequence of Events” on page 76 for more information. 1 A9 2 A10 3 A11 / T3 4 A12 / T4 5 A13 / T4 6 A14 / T6 7 A15 / T7 |
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