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ISO7721FD Datasheet(PDF) 19 Page - Texas Instruments |
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ISO7721FD Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 42 page  19 ISO7720, ISO7721 www.ti.com SLLSEP3C – NOVEMBER 2016 – REVISED JULY 2018 Product Folder Links: ISO7720 ISO7721 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated (1) See the Safety-Related Certifications section for detailed isolation ratings. 8.3 Feature Description The ISO772x family of devices is available in two channel configurations and default output state options to enable a variety of application uses. Table 1 lists the device features of the ISO772x devices. Table 1. Device Features PART NUMBER MAXIMUM DATA RATE CHANNEL DIRECTION DEFAULT OUTPUT STATE PACKAGE RATED ISOLATION(1) ISO7720 100 Mbps 2 Forward, 0 Reverse High DW-16 5000 VRMS / 8000 VPK DWV-8 5000 VRMS / 7071 VPK D-8 3000 VRMS / 4242 VPK ISO7720F 100 Mbps 2 Forward, 0 Reverse Low DW-16 5000 VRMS / 8000 VPK DWV-8 5000 VRMS / 7071 VPK D-8 3000 VRMS / 4242 VPK ISO7721 100 Mbps 1 Forward, 1 Reverse High DW-16 5000 VRMS / 8000 VPK DWV-8 5000 VRMS / 7071 VPK D-8 3000 VRMS / 4242 VPK ISO7721F 100 Mbps 1 Forward, 1 Reverse Low DW-16 5000 VRMS / 8000 VPK DWV-8 5000 VRMS / 7071 VPK D-8 3000 VRMS / 4242 VPK 8.3.1 Electromagnetic Compatibility (EMC) Considerations Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO772x family of devices incorporates many chip-level design improvements for overall system robustness. Some of these improvements include: • Robust ESD protection cells for input and output signal pins and inter-chip bond pads. • Low-resistance connectivity of ESD cells to supply and ground pins. • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events. • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path. • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs. • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation. |
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