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NTE6508 Datasheet(PDF) 2 Page - NTE Electronics

Part No. NTE6508
Description  Integrated Circuit CMOS, 1K Static RAM (SRAM)
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Maker  NTE [NTE Electronics]
Homepage  http://www.nteinc.com
Logo NTE - NTE Electronics

NTE6508 Datasheet(HTML) 2 Page - NTE Electronics

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DC Electrical Characteristics: VCC = 5V ±10%, TA = –40° to +85°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Standby Supply Current
ICC(SB)
IO = 0, VI = VCC or GND, VCC = 5V
10
µA
Operating Supply Current
ICC(OP)
E = 1MHz, IO = 0, VI = VCC or GND,
VCC = 5.5V, Note 2
4
mA
Data Retention Supply Current
ICC(DR)
VCC = 2V, IO = 0, VI = VCC or GND,
E = VCC
10
µA
Data Retention Supply Voltage
VCC(DR)
2.0
V
Input Leakage Current
II
VI = VCC or GND, VCC = 5.5V
–1.0
+1.0
µA
Output Leakage Current
IOZ
VO = VCC or GND, VCC = 5.5V
–1.0
+1.0
µA
Input Voltage, LOW
VIL
VCC = 4.5V
–0.3
+0.8
V
Input Voltage, HIGH
VIH
VCC = 5.5V
VCC–2
VCC+0.3
V
Output Voltage, LOW
VOL
IO = 3.2mA, VCC = 4.5V
0.4
V
Output Voltage, HIGH
VOH
IO = –0.4mA, VCC = 4.5V
2.4
V
Note 2. Typical derating 1.5mA/MHz increase in ICC(OP).
Capacitance: (TA = +25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Capacitance
CI
f = 1MHz, All measurements are ref-
6
pF
Output Capacitance
CO
erenced to device GND
10
pF
AC Electrical Characteristics: VCC = 5V ±10%, TA = –40° to +85°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Chip Enable Access Time
TELQV
Note 3, Note 5
300
ns
Address Access Time
TAVQV
Note 3, Note 5, & Note 6
300
ns
Chip Enable Output Enable Time
TELQX
Note 4, Note 5
5
160
ns
Write Enable Output Disable Time
TWLQZ
Note 4, Note 5
160
ns
Chip Enable Output Disable Time
TEHQZ
Note 4, Note 5
160
ns
Chip Enable Pulse Negative Width
TELEH
Note 3, Note 5
300
ns
Chip Enable Pulse Positive Width
TEHEL
Note 3, Note 5
100
ns
Address Setup Time
TAVEL
Note 3, Note 5
0
ns
Address Hold Time
TELAX
Note 3, Note 5
50
ns
Data Setup Time
TDVWH
Note 3, Note 5
110
ns
Data Hold Time
TWHDX
Note 3, Note 5
0
ns
Chip Enable Write Pulse Setup Time
TWLEH
Note 3, Note 5
130
ns
Chip Enable Write Pulse Hold Time
TELWH
Note 3, Note 5
130
ns
Write Enable Pulse Width
TWLWH Note 3, Note 5
130
ns
Read or Write Cycle Time
TELEL
Note 3, Note 5
350
ns
Note 3. Input pulse levels: 0.8V to VCC –2V; Input rise and fall times: 5ns (max); Input and output
timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) – for CL
greater than 50pF, access time is derated by 0.15ns per pF.
Note 4. Tested at initial design and after major design changes.
Note 5. VCC = 4.5V and 5.5V.
Note 6. TAVQV = TELQV + TAVEL.


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