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ADL5335 Datasheet(PDF) 6 Page - Analog Devices |
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ADL5335 Datasheet(HTML) 6 Page - Analog Devices |
6 / 16 page ADL5335 Data Sheet Rev. 0 | Page 6 of 16 DIGITAL LOGIC TIMING Table 2. Parameter Description Min Typ Max Unit tCLK Maximum serial clock rate 25 MHz tHI Minimum period that SCLK is in a logic high state 10 ns tLO Minimum period that SCLK is in a logic low state 10 ns tS Setup time between falling edge of CS and SCLK 15 ns tH Hold time between data and rising edge of SCLK 5 ns tDS Setup time between data and rising edge of SCLK 15 ns tDH SCLK to SDIO Hold Time 10 ns tZ Maximum time delay between CS deactivation and SDIO bus to return to high impedance 5 ns tACCESS Maximum time delay between falling edge of SCLK and out data valid for a read operation 5 ns SPI Timing Diagram CS SCLK SDIO DON’T CARE DON’T CARE R/W A14 A13 A12 A11 A10 A9 D7 D6 D5 D4 D3 D2 D1 D0 DON’T CARE DON’T CARE tS tDH tDS tHI tLO tCLK tACCESS tH tZ Figure 2. SPI Timing |
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