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SMJ44C251 Datasheet(PDF) 8 Page - Texas Instruments |
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SMJ44C251 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 53 page  SMJ44C251B 262144 BY 4-BIT MULTIPORT VIDEO RAM SGMS058A – MARCH 1995 – REVISED JUNE 1995 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 random-access operation The random-access operation functions are summarized in Table 2 and described in the following sections. Table 2. Random-Access-Operation Functions FUNCTION RAS FALL CAS FALL ADDRESS DQ0 – DQ3 FUNCTION CAS TRG W† DSF SE DSF RAS CAS RAS CAS‡ W CBR refresh L X X X X X X X X X Load and use write mask, Write data to DRAM H H L L X L Row Addr Col Addr DQ Mask Valid Data Load and use write mask, Block write to DRAM H H L L X H Row Addr Blk Addr A2 – A8 DQ Mask Col Mask Persistent write-per-bit, Write data to DRAM H H L H X L Row Addr Col Addr X Valid Data Persistent write-per-bit, Block write to DRAM H H L H X H Row Addr Blk Addr A2 – A8 X Col Mask Normal DRAM read / write (nonmasked) H H H L X L Row Addr Col Addr X Valid Data Block write to DRAM (nonmasked) H H H L X H Row Addr Blk Addr A2 – A8 X Col Mask Load write mask H H H H X L Refresh Addr X X DQ Mask Load color register H H H H X H Refresh Addr X X Color Data Legend: H = High L = Low X = Don’t care † In persistent write-per-bit function, W must be high during the refresh cycle. ‡ DQ0 – DQ3 are latched on the later of W or CAS falling edge. Col Mask = H: Write to address/column location enabled DQ Mask = H: Write to I/O enabled enhanced page mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. This mode eliminates the time required for row address setup-and-hold and address multiplex. The maximum RAS low time and the CAS page cycle time used determine the number of columns that can be accessed. Unlike conventional page-mode operation, the enhanced page mode allows the SMJ44C251B to operate at a higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CAS transitions low. A valid column address can be presented immediately after row-address hold time has been satisfied, usually well in advance of the falling edge of CAS. In this case, data can be obtained after ta(C) max (access time from CAS low), if ta(CA) max (access time from column address) has been satisfied. refresh There are three types of refresh available on the SMJ44C251B: RAS-only refresh, CBR refresh, and hidden refresh. |
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