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SAA7115 Datasheet(PDF) 83 Page - NXP Semiconductors |
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SAA7115 Datasheet(HTML) 83 Page - NXP Semiconductors |
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83 / 214 page  Confidential - NDA required page 83 Filename: SAA7115_Datasheet.fm Last edited by H. Lambers Philips Semiconductors CVIP2 Date: 10/23/01 CS-PD Hamburg Datasheet SAA7115 Version: 0.67 Table 28 Programming examples for audio master clock generation (no CGC2 support) 8.7.1.2 Signals ASCLK and ALRCLK Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for channel-select. The frequencies of these signals are defined by the following parameters: • SDIV[5:0] 38H[5:0] according to the equation: ⇒ • LRDIV[5:0] 39H[5:0] according to the equation: ⇒ See Table 29 for examples. XTALO (MHz) FIELD (Hz) ACPF ACNI DECIMAL HEX DECIMAL HEX AMCLK = 256 × 48 kHz (12.288 MHz) 32.11 50 245760 3C000 3210190 30FBCE 59.94 205005 320CD 3210190 30FBCE 24.576 50 −−−− 59.94 −−−− AMCLK = 256 × 44.1 kHz (11.2896 MHz) 32.11 50 225792 37200 2949362 2D00F2 59.94 188348 2DFBC 2949362 2D00F2 24.576 50 225792 37200 3853517 3ACCCD 59.94 188348 2DFBC 3853 517 3ACCCD AMCLK = 256 × 32 kHz (8.192 MHz) 32.11 50 163840 28000 2140127 20A7DF 59.94 136670 215DE 2140127 20A7DF 24.576 50 163840 28000 2796203 2AAAAB 59.94 136670 215DE 2796203 2AAAAB f ASCLK f AMXCLK SDIV 1 + () 2 × -------------------------------------- = SDIV[5:0] f AMXCLK 2f ASCLK -------------------- 1 – = f ALRCLK f ASCLK LRDIV 2 × --------------------------- = LRDIV[5:0] f ASCLK 2f ALRCLK ----------------------- = |
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