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EM6682 Datasheet(PDF) 11 Page - EM Microelectronic - MARIN SA

Part # EM6682
Description  Ultra Low Power 8-pin Microcontroller
Download  59 Pages
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Manufacturer  EMMICRO [EM Microelectronic - MARIN SA]
Direct Link  http://www.emmicroelectronic.com
Logo EMMICRO - EM Microelectronic - MARIN SA

EM6682 Datasheet(HTML) 11 Page - EM Microelectronic - MARIN SA

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EM6682
Copyright
2008, EM Microelectronic-Marin SA
04/08
– rev.D
11
www.emmicroelectronic.com
5. Oscillator and Prescaler
5.1 RC Oscillator or external Clock
EM6682 can use the internal RC oscillator or external clock source for its operation.
The built-in RC oscillator without external components generates the system operating clock for the CPU and peripheral
blocks. The RC oscillator is supplied by the regulated voltage in medium voltage version.
The RC oscillator can generate 2 basic frequencies selectable by metal option or by registers 512kHz or 800kHz selected by
RegMFP1[3].
In the output of the RC oscillator, a selectable divider allows generating 512kHz, 256kHz, 128kHz, 64kHz or 32kHz. If the
basic frequency is 800kHz the divider can generate 800kHz, 400kHz, 200kHz, 100kHz or 50kHz. The division factor is given
by the register RegMFP1[2:0] (see table 5.2.1). These frequencies can be used for the CPU clock (if the external clock is not
selected). Another divider generates automatically SysClk as close as possible to 32kHz or 50kHz depending on the basic
frequency selected. This clock is used by the 15 stages prescaler that generated clock for the peripherals.
For a full software compatibility with the EM6680 and EM6681, the division factor of the RC clock can be fix by metal option.
It means that it is not necessary to set the RC frequency by software. To get a good frequency stability over the supply in
low voltage it is possible, by metal option, to select a 128kHz (or 200kHz) RC oscillator. In this case the division
factor is fixed to 1 meaning that the CPU runs at 128kHz (or 200kHz) and SysClk at 32kHz (or 50kHz). It is not
permitted to use the EM6682 at LV over 128kHz (200kHz).
Please note that Vddmin must be higher when working with higher frequencies – see figure 30.
After POR the circuit always starts with the internal RC oscillator, but it can be switched to the external clock by setting the
ExtCPUclkON bit in the register RegPresc. The external clock is input at PA[1] and must be in range from min. 10Khz to
max. 1MHz. With this external frequency input all timing for peripherals change and the special 4 stage freq. divider must be
adapted to best suit the applied external frequency to keep 32/50kHz System clock as close as possible. The system clock
must be less than 64kHz. The external clock source must be a square wave with full amplitude from Vss to Vdd. See Table
5.2.2 for advised special divisions depending on the external clock frequency.
Switching from internal RC oscillator to External clock or back from External clock to RC oscillator is made without generating
a glitch on the internal clock. Once the circuit is running on the external Clock one can disable the RC oscillator by settin g the
RCoscOff bit in RegSCntl2
to „1‟.
In sleep mode the oscillator is stopped. It can be stopped also by setting the RCoscOff bit. This bit can be set only if
ExtClkOn was set before, indicating that the CPUck was switched from the internal RC oscillator to the external clock which
MUST be present. If the External Clock stops without going into Sleep mode first the EM6682 can block and only POR can
reset it.
Figure 8 below shows the connection of the RC oscillator and external clock and generation of CPUclk and System clock =
SysClk which is divided by the special 4 stage Freq. Divider if needed as described in
97H
5.2 and prescaler described in 5.3.
Figure 8. Clock source for CPU or system peripherals
MUX
RegOscTrim1
[3:0]
RegOscTrim1
[3:0]
RC oscilator
512kHz
– 800kHz
OscTrim[7:0]
RegMFP1
[3]
RegMFP1
[2:0]
Frequency
divider
MUX
Metal option
or register
selector
Metal option
or register
selector
RC SYSTEM
External clock
10kHz
– 1MHz
ExtCPUclkON
Frequency
divider
MUX
Automatic clock selection
SysClk = 32kHz or 50kHz
CPUclk
PRESCALER
LOW 15 stages divider
MUX
foutSel[1:0]
MUX
Sout
PAout[2]
ResSys
PA[2]
Peripherals
SysClk
Ck[14]
MUX
PAout[2]
PA[5]
PA[1]


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