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TW6872 Datasheet(PDF) 27 Page - Renesas Technology Corp |
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TW6872 Datasheet(HTML) 27 Page - Renesas Technology Corp |
27 / 44 page TW6872 FN8616 Rev 0.00 Page 27 of 44 May 23, 2014 3 ISPCLK_DIV10_SEL Selects CLKO divider relationship 0: Divide by 20 1: Divide by 10 0 2 ISPCLK_XTALCLK_SEL Select XTI clock on to ISP clock 0: Select Div10/20 transmit clock for ISP clock 1: Select XTI clock for ISP clock 0 1:0 IFPLL_REFSEL Selects the IFPLL reference from the XTI input, INPLL output, or from divided VD_CLK 0x0 TABLE 12. PLL_CTRL: PLL CONTROL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ-WRITE, DEFAULT=0x00, ADDR=0x080 (Continued) BIT NAME BIT DEFINITION DEFAULT TABLE 13. IFPLLMDIV: INTERMEDIATE PLL M DIVIDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ-WRITE, DEFAULT=0x00, ADDR=0x081 BIT NAME BIT DEFINITION DEFAULT 7 RESERVED Reserved 0 6:0 IFPLLM2DIV IFPLL M-divider from 9 to 128 0x0 TABLE 14. TXPLLPDIV: TRANSMIT PLL POST DIVIDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ-WRITE, DEFAULT=0x00, ADDR=0x082 BIT NAME BIT DEFINITION DEFAULT 7 RESERVED Reserved 0 6:0 TXPLLP2DIV Transmit PLL post divider from 1 to 128 0x0 TABLE 15. IFD: INTERMEDIATE FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ-WRITE, DEFAULT=0x00, ADDR=0x083 BIT NAME BIT DEFINITION DEFAULT 7 RESERVED Reserved 0 6:0 IFD Divider to select the intermediate frequency in the TXPLL if two PLLs are used for cascading to improve performance. This is used as both the P-divider of the IFPLL and the M-divider of the TXPLL. Because of this, the IFPLL and TXPLL VCO are always running at the same frequency, unless one of them is turned off. Valid values are 9 to 128. 0x0 TABLE 16. PLLTRIM_0: PLL TRIM 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ-WRITE, DEFAULT=0x00, ADDR=0x084 BIT NAME BIT DEFINITION DEFAULT 7:0 PLLTRIM0 PLL trim 0. PLLTRIM[7:0]. Recommend setting PLLTRIM[7] = 1. 0x0 TABLE 17. PLLTRIM_1: PLL TRIM 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ-WRITE, DEFAULT=0x00, ADDR=0x085 BIT NAME BIT DEFINITION DEFAULT 7 RESERVED Reserved 0 6:4 INPLLNDIV INPLL N (reference input) divider. Used to divide the VD_CLK input before applying it as a reference for the INPLL. 0x0 3 RESERVED Reserved 0 2:0 PLLTRIM1 PLL trim 1. PLLTRIM[10:8]. Recommend setting PLLTRIM[10:8] = 0x7. 0x0 TABLE 18. INPLLMDIV: INPUT PLL M DIVIDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ-WRITE, DEFAULT=0x00, ADDR=0x086 BIT NAME BIT DEFINITION DEFAULT 7 RESERVED Reserved 0 6:0 INPLLM1DIV Input PLL M-divider from 9 to 128 0x0 TABLE 19. INPLLPDIV: INPUT PLL POST DIVIDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ-WRITE, DEFAULT=0x00, ADDR=0x087 BIT NAME BIT DEFINITION DEFAULT 7 RESERVED Reserved 0 6:0 INPLLP1DIV Input PLL post divider from 9 to 128 0x0 |
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