TW6872

FN8616 Rev 0.00

Page 26 of 44

May 23, 2014

TABLE 8. MISC_CTRL: MISCELLANEOUS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .READ-WRITE, DEFAULT=0x00, ADDR=0x016

BIT

NAME

BIT DEFINITION

DEFAULT

7:6

RESERVED

Reserved

0

5

ALT10EN

Enable 1-0-1-0 pattern

0: Normal operation

1: Enable 1-0-1-0 pattern

0

4

PRBSRATE

Select PRBS rate

0: HD/3G

1: SD

0

3

PRBSPAT

Select PRBS polynomial

0: PRBS23

1: PRBS7

0

2

PRBSEN

Enable PRBS pattern

0: Normal operation

1: Enable PRBS pattern

0

1

DATATHRU

Enable data through mode (data is not SDI encoded)

0: Normal operation

1: Enable data through mode

0

0

ASIEN

Enable ASI

0: Normal operation

1: Enable ASI

0

TABLE 9. ACLK_CTRL: AUDIO CLOCK CONTROL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .READ-WRITE, DEFAULT=0x00, ADDR=0x017

BIT

NAME

BIT DEFINITION

DEFAULT

7:2

RESERVED

Reserved

0x0

1

ACLKINV

Audio clock invert

0: Not inverted

1: Inverted

0

0

ACLKSEL

Audio clock selection

0: ACLK pin is audio clock input

1: Use internally generated audio clock

0

TABLE 10. VC2_CTRL: VC2 CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ-WRITE, DEFAULT=0x00, ADDR=0x018

BIT

NAME

BIT DEFINITION

DEFAULT

7:0

RESERVED

Reserved

0x0

TABLE 11. STATUS: STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ-ONLY, ADDR=0x01F

BIT

NAME

BIT DEFINITION

DEFAULT

7:1

RESERVED

Reserved

0x0

0

VC2STATE

Live state of OPT_DIRAC_PD pin

0

TABLE 12. PLL_CTRL: PLL CONTROL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ-WRITE, DEFAULT=0x00, ADDR=0x080

BIT

NAME

BIT DEFINITION

DEFAULT

7

RESERVED

Reserved

0

6

INPLL_REFSEL

Selects INPLL clock source

0: From XTI input

1: From divided VD_CLK input

0

5

PCLK_DIV10_SEL

Sets PISO clock divider relationship to the SDI transmit clock

0: Divide by 20

1: Divide by 10

0

4

VC2_CLKSEL

Select the SDI shift register clock from INPLL or TXPLL

0: Select TXPLL clock

1: Select INPLL 270MHz clock

0