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ML87V2104 Datasheet(PDF) 5 Page - OKI electronic componets

Part No. ML87V2104
Description  Video Signal Noise Reduction and Field Rate Conversion IC with a Built-in 4M Bit Field Memory
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Maker  OKI [OKI electronic componets]
Homepage  http://www.oki.com
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ML87V2104 Datasheet(HTML) 5 Page - OKI electronic componets

 
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PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
5/13
No.
Symbol
I/O
Pad Remarks
Pin Description
42
VDD
Power supply 3.3 V
43
DNR
I
pull-down 50k
Noise reduction output mode setting pin
0: Normal operation
1: Direct noise reduction mode
44
N.C.
Unused pin
45
SSG
I
pull-down 50k
Internally generated sync signal mode setting pin
46
INT
I
pull-down 50k
Output system sync signal input/output select setting pin
0: OVS, OHS input mode
1: OVS, OHS internally generated output mode
47
OHS
I/O
Schmitt(IN)
pull-down 50k
Output system horizontal sync signal input/output pin
48
OVS
I/O
Schmitt(IN)
pull-down 50k
Output system vertical sync signal input/output pin
49
HREF
O
Data output horizontal reference signal output pin
50
VSS
Ground
51
VDD
Power supply 3.3 V
52
CO0
O
Chrominance signal output pin – bit 0 (LSB)
53
CO1
O
Chrominance signal output pin – bit 1
54
CO2
O
Chrominance signal output pin – bit 2
55
CO3
O
Chrominance signal output pin – bit 3
56
VSS
Ground
57
CO4
O
Chrominance signal output pin – bit 4
58
CO5
O
Chrominance signal output pin – bit 5
59
CO6
O
Chrominance signal output pin – bit 6
60
CO7
O
Chrominance signal output pin – bit 7(MSB)
61
VDD
Ground
62
OCLK
I
Output system clock pin
63
VSS
Ground
64
YO0
O
Luminance signal output pin – bit 0 (LSB)
65
YO1
O
Luminance signal output pin – bit 1
66
YO2
O
Luminance signal output pin – bit 2
67
YO3
O
Luminance signal output pin – bit 3
68
VDD
Power supply 3.3 V
69
YO4
O
Luminance signal output pin – bit 4
70
YO5
O
Luminance signal output pin – bit 5
71
YO6
O
Luminance signal output pin – bit 6
72
YO7
O
Luminance signal output pin – bit 7 (MSB)
73
VSS
Ground
74
N.C.
Unused pin
75
N.C.
Unused pin
76
N.C.
Unused pin
77
N.C.
Unused pin
78
N.C.
Unused pin
79
RESET
I
System reset input pin (0 active)
0: System reset 1: Normal operation
Apply ICLK cycle one and more time during “0” level after VDD
voltage has reached the specified level in System reset operation.


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