KAD5512HP

FN6808 Rev 4.00

Page 28 of 34

May 31, 2016

C0

Test_io

User Test Mode [1:0]

00 = Single

01 = Alternate

10 = Reserved

11 = Reserved

Output Test Mode [3:0]

00h

G

0 = Off

1 = Midscale

Short

2 = +FS Short

3 = -FS Short

4 = Checker

Board

5 = Reserved

6 = Reserved

7 = One/Zero Word

Toggle

8 = User Input

9-15 = Reserved

C1

Reserved

Reserved

00h

G

C2

User_Patt 1_LSB

B7

B6

B5

B4

B3

B2

B1

B0

00h

G

C3

User_Patt1_MSB

B15

B14

B13

B12

B11

B10

B9

B8

00h

G

C4

User_Patt 2_LSB

B7

B6

B5

B4

B3

B2

B1

B0

00h

G

C5

User_Patt2_MSB

B15

B14

B13

B12

B11

B10

B9

B8

00h

G

C6-FF

Reserved

Reserved

NOTE:

15. At power-up, the DDR Enable bit is at a logic ‘0’ for the 72 Ld package and set to a logic ‘1’ internally for the 48 Ld package by an internal pull-up.

ADDR

(Hex)

PARAMETER

NAME

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

DEF. VALUE

(Hex)

INDEXED/

GLOBAL

Equivalent Circuits

FIGURE 42. ANALOG INPUTS

FIGURE 43. CLOCK INPUTS

AVDD

INP

INN

AVDD

F1

F1

F2

F 3

F2

F 3

CSAMP

1.6pF

CSAMP

1.6pF

TO

CHARGE

PIPELINE

TO

CHARGE

PIPELINE

1000O

Ω













AVDD

CLKP

CLKN

AVDD

AVDD

TO

CLOCK-

PHASE

GENERATION

11kO

11kO

AVDD

18kO

18kO

Ω

Ω

Ω

Ω