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KAD5512P-50 Datasheet(PDF) 26 Page - Renesas Technology Corp |
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KAD5512P-50 Datasheet(HTML) 26 Page - Renesas Technology Corp |
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26 / 34 page  KAD5512HP FN6808 Rev 4.00 Page 26 of 34 May 31, 2016 Internal clock signals are generated by a Delay-Locked Loop (DLL), which has a finite operating range. Table 15 shows the allowable sample rate ranges for the slow and fast settings. The output_mode_B and config_status registers are used in conjunction to enable DDR mode and select the frequency range of the DLL clock generator. The method of setting these options is different from the other registers. The procedure for setting output_mode_B is shown in Figure 41. Read the contents of output_mode_B and config_status and XOR them. Then XOR this result with the desired value for output_mode_B and write that XOR result to the register. Device Test The KAD5512HP can produce preset or user defined patterns on the digital outputs to facilitate in situ testing. A static word can be placed on the output bus, or two different words can alternate. In the alternate mode, the values defined as Word 1 and Word 2 (as shown in Table 16) are set on the output bus on alternating clock phases. The test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus. ADDRESS 0XC0: TEST_IO Bits 7:6 User Test Mode These bits set the test mode to static (0x00) or alternate (0x01) mode. Other values are reserved. The four LSBs in this register (Output Test Mode) determine the test pattern in combination with registers 0xC2 through 0xC5. Refer to Table 16. ADDRESS 0XC2: USER_PATT1_LSB ADDRESS 0XC3: USER_PATT1_MSB These registers define the lower and upper eight bits, respectively, of the first user-defined test word. ADDRESS 0XC4: USER_PATT2_LSB ADDRESS 0XC5: USER_PATT2_MSB These registers define the lower and upper eight bits, respectively, of the second user-defined test word. TABLE 15. DLL RANGES DLL RANGE MIN MAX UNIT Slow 40 100 MSPS Fast 80 fS MAX MSPS FIGURE 41. SETTING OUTPUT_MODE_B REGISTER READ CONFIG_STATUS 0x75 READ OUTPUT_MODE_B 0x74 DESIRED VALUE WRITE TO 0x74 TABLE 16. OUTPUT TEST MODES VALUE 0xC0[3:0] OUTPUT TEST MODE WORD 1 WORD 2 0000 Off 0001 Midscale 0x8000 N/A 0010 Positive Full-Scale 0xFFFF N/A 0011 Negative Full-Scale 0x0000 N/A 0100 Checkerboard 0xAAAA 0x5555 0101 Reserved N/A N/A 0110 Reserved N/A N/A 0111 One/Zero 0xFFFF 0x0000 1000 User Pattern user_patt1 user_patt2 |
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