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KAD5512P-50 Datasheet(PDF) 28 Page - Renesas Technology Corp |
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KAD5512P-50 Datasheet(HTML) 28 Page - Renesas Technology Corp |
28 / 30 page KAD5510P-50 FN6811 Rev 3.00 Page 28 of 30 May 31, 2016 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE May 31, 2016 FN6811.3 Increased maximum currents and NAP power dissipation as follows: IAVDD Max from 178 to 188 NAP mode power Max from 163 to 170.2 Updated 163 to 170.2 in “Nap/Sleep” on page 17. Added About Intersil section. May 8, 2009 FN6811.2 1)Added nap mode, sleep mode wake up times to spec table 2) Added CSB,SCLK Setup time specs for nap,sleep modes to spec table 3) Changed SPI setup spec wording in spec table 4) Change to pin description table for clarification 5) Added thermal pad note 6) Updated fig 23 and fig 24 and description in text. 7) Update multiple device usage note on at “SPI Physical Interface” on page 20 8) Added ‘Reserved’ to SPI memory map at address 25H 9) Added section on “ADC Evaluation Platform” on page 26 10) Updated table “DIFFERENTIAL SKEW ADJUSTMENT” on page 22. 11) Intersil Standards - Added Pb-free reflow link 12) Changed to SPI interface section in spec table, timing in cycles now, added write, read specific timing specs. 13) Updated SPI timing diagrams, Figures 35, 36 14) Updated wakeup time description in “Nap/Sleep” on page 17. 15) Updated sleep mode power spec 16) Changed label in Figure 44 17) Updated cal paragraph in user initiated reset section per DC Changed standard over-temp from “Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested” TO “Parameters with Min and/or MAX limits are 100% production tested at their worst case temperature extreme (+85°C) per Jeff Rogers and Gary Hendrickson.” Updated Note references in Electrical Spec Table. January 19, 2009 FN6811.1 P1; revised Key Specs P2; added Part Marking column to Order Info P4; Moved Thermal Impedance under Thermal Info (used to be on p. 7). Added Theta JA Note 2. P4-7; edits throughout the Specs table. Added Notes 8 and 9. Revised Notes 6 and 7. P7; Removed ESD section P10-12; revised Performance Curves throughout P14; User Initiated Reset section; revised 2nd sentence of 1st paragraph P16; Nap/Sleep; revised 3rd and 4th sentences of 1st paragraph P19; Serial Peripheral Interface; revised 2nd to last sentence of 1st paragraph. SPI Physical Interface; revised 2nd and 3rd sentences of 4th paragraph P20; added last 2 sentences to 1st paragraph of "ADDRESS 0X24: GAIN_FINE". Revised Table 8 P21; revised last 2 sentences of "ADDRESS 0X71: PHASE_SLIP". Removed Figure of "PHASE SLIP: CLK÷1 MODE, fCLOCK = 500MHz" P24; revised Figure 43 P24; Table 17; revised Bits7:4, Addr C0 Throughout; formatted graphics to Intersil standards August 6, 2008 FN6811.1 Initial Release December 5, 2008 FN6811.0 Converted to intersil template. Assigned file number FN6811. Rev 0 - first release (as preliminary datasheet) with new file number. |
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