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KAD2710C Datasheet(PDF) 14 Page - Renesas Technology Corp

Part No. KAD2710C
Description  10-Bit, 275/210/170/105MSPS A/D Converter
Download  16 Pages
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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KAD2710C Datasheet(HTML) 14 Page - Renesas Technology Corp

 
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FN6814 Rev 0.00
Page 14 of 16
December 5, 2008
KAD2710C
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2008. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1. The internal aperture jitter combines with the input
clock jitter in a root-sum-square fashion, since they are not
statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Digital Outputs
Data is output on a parallel bus with LVCMOS drivers.
The output format (Binary or Two’s Complement) is selected
via the 2SC pin as shown in Table 3.
TABLE 3. 2SC PIN SETTINGS
2SC PIN
MODE
AVSS
Two’s Complement
AVDD (or unconnected)
Binary
Equivalent Circuits
FIGURE 28. ANALOG INPUTS
FIGURE 29. CLOCK INPUTS
FIGURE 30. LVCMOS OUTPUTS
AVDD3
INP
INN
AVDD3
F1
F1
F2
Csamp
0.3pF
To
Charge
Pipeline
2pF
2pF
F2
Csamp
0.3pF
To
Charge
Pipeline
AVDD2
CLKP
CLKN
AVDD2
AVDD2
To Clock
Generation
D[9:0]
OVDD
OVDD
DATA


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