KAD2710C

FN6814 Rev 0.00

Page 13 of 16

December 5, 2008

A back-to-back transformer scheme is used to improve

common-mode rejection, which keeps the common-mode level

should be determined based on the desired load impedance.

The sample and hold circuit design uses a switched capacitor

input stage, which creates current spikes when the sampling

capacitance is reconnected to the input voltage. This creates a

disturbance at the input which must settle before the next

sampling point. Lower source impedance will result in faster

settling and improved performance. Therefore a 1:1

transformer and low shunt resistance are recommended for

optimal performance.

A differential amplifier can be used in applications that require

dc coupling. In this configuration the amplifier will typically

determine the achievable SNR and distortion. A typical

differential amplifier circuit is shown in Figure 25.

Clock Input

The sample clock input circuit is a differential pair (see Figure

each input) sine or square wave will provide the lowest jitter

performance.

The recommended drive circuit is shown in Figure 26. The

clock can be driven single-ended, but this will reduce the edge

rate and may impact SNR performance.

Use of the clock divider is optional. The KAD2710C's ADC

requires a clock with 50% duty cycle for optimum performance.

If such a clock is not available, one option is to generate twice

the desired sampling rate and use the KAD2710C's divide-by-2

setting. This frequency divider uses the rising edge of the

clock, so 50% clock duty cycle is assured. Table 2 describes

the CLKDIV connection.

CLKDIV is internally pulled low, so a pull-up resistor or logic

driver must be connected for undivided clock.

Jitter

In a sampled data system, clock jitter directly impacts the

achievable SNR performance. The theoretical relationship

illustrated in Figure 27.

FIGURE 23. TRANSFORMER INPUT FOR GENERAL

APPLICATIONS

ADT1-1WT

0.1µF

KAD2710

VCM

50

O

0.01µF

Analog

In

ADT1-1WT



ADTL1-12

0.1µF

KAD2710

VCM

ADTL1-12

1nF

1nF

Analog

Input

FIGURE 24. TRANSMISSION-LINE TRANSFORMER INPUT

FOR HIGH IF APPLICATIONS

KAD2710

VCM

0.1µF

0.22µF

69.8O

49.9O

100O

100O

69.8O

348O

348O

CM

217O

25O

25O

Analog

Input

FIGURE 25. DIFFERENTIAL AMPLIFIER INPUT





















TABLE 2. CLKDIV PIN SETTINGS

CLKDIV PIN

DIVIDE RATIO

AVSS

2

AVDD

1

TC4-1W

1nF

AVDD2

200O

CLKP

CLKN

1kO

1kO

1nF

Clock

Input

FIGURE 26. RECOMMENDED CLOCK DRIVE







SNR

1

2

f

--------------------





=

(EQ. 1)

tj=100p s

tj=10p s

tj=1ps

tj=0.1p s

10 Bits

12 Bits

14 Bits

50

55

60

65

70

75

80

85

90

95

100

1

10

100

1000

Input Frequency - MHz

FIGURE 27. SNR vs CLOCK JITTER