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K6F8016V3A-F Datasheet(PDF) 5 Page - Samsung semiconductor |
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K6F8016V3A-F Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 9 page K6F8016V3A Family Revision 1.0 September 2001 5 CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL DATA RETENTION CHARACTERISTICS 1. CS1 ≥Vcc-0.2V,CS2 ≥Vcc-0.2V(CS1 controlled) or CS2≥Vcc-0.2V(CS2 controlled). 2. Typical value are measured at TA=25 °C and not 100% tested. Item Symbol Test Condition Min Typ2) Max Unit Vcc for data retention VDR CS1 ≥Vcc-0.2V1) 1.5 - 3.6 V Data retention current IDR Vcc=1.5V, CS1 ≥Vcc-0.2V1) - 0.5 6 µA Data retention set-up time tSDR See data retention waveform 0 - - ns Recovery time tRDR tRC - - AC CHARACTERISTICS (Vcc=3.0~3.6V) Parameter List Symbol Speed Bins Units 55ns 70ns Min Max Min Max Read Read Cycle Time tRC 55 - 70 - ns Address Access Time tAA - 55 - 70 ns Chip Select to Output tCO - 55 - 70 ns Output Enable to Valid Output tOE - 25 - 35 ns UB, LB Access Time tBA - 25 - 35 ns Chip Select to Low-Z Output tLZ 10 - 10 - ns UB, LB Enable to Low-Z Output tBLZ 5 - 5 - ns Output Enable to Low-Z Output tOLZ 5 - 5 - ns Chip Disable to High-Z Output tHZ 0 20 0 25 ns UB, LB Disable to High-Z Output tBHZ 0 20 0 25 ns Output Disable to High-Z Output tOHZ 0 20 0 25 ns Output Hold from Address Change tOH 10 - 10 - ns Write Write Cycle Time tWC 55 - 70 - ns Chip Select to End of Write tCW 45 - 60 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 45 - 60 - ns UB, LB Valid to End of Write tBW 45 - 60 - ns Write Pulse Width tWP 40 - 50 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 20 0 20 ns Data to Write Time Overlap tDW 25 - 30 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - ns CL1) 1. Including scope and jig capacitance R22) R12) VTM3) 2. R1=3070 Ω, R2=3150Ω 3. VTM =2.8V |
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