Data Sheet

ADN2805

Rev. B | Page 13 of 16

SQUELCH MODE

Two squelch modes are available with the ADN2805. The

SQUELCH DATAOUT and CLKOUT mode is selected when

CTRLC[1] = 0 (default mode). In this mode, when the SQUELCH

input, Pin 27, is driven to a TTL high state, both the clock and

data outputs are set to the zero state to suppress downstream pro-

cessing. If the squelch function is not required, tie Pin 27 to VEE.

SQUELCH DATAOUT or CLKOUT mode is selected when

CTRLC[1] is 1. In this mode, when the SQUELCH input is

driven to a high state, the DATAOUTN/DATAOUTP pins

are squelched. When the SQUELCH input is driven to a low

state, the CLKOUT pins are squelched. This feature is especially

useful in repeater applications, where the recovered clock may

not be needed.

SYSTEM RESET

A frequency acquisition can be initiated by writing a 1 followed

frequency acquisition while keeping the ADN2805 in the

operating mode that it was previously programmed to in

Register CTRL[A], Register CTRL[B], and Register CTRL[C].

driving multiple peripherals. Two inputs, serial data (SDA) and

serial clock (SCK), carry information between any devices

connected to the bus. Each slave device is recognized by a

unique address. The ADN2805 has two possible 7-bit slave

addresses for both read and write operations. The MSB of the

7-bit slave address is factory programmed to 1. Bit 5 of the slave

address is set by Pin 19, SADDR5. Slave Address Bits[4:0] are

defaulted to all 0s. The slave address consists of the 7 MSBs of

an 8-bit word. The LSB of the word either sets a read or write

operation (see Figure 6). Logic 1 corresponds to a read

operation whereas Logic 0 corresponds to a write operation.

To control the device on the bus, the following protocol must be

followed. First, the master initiates a data transfer by establishing

a start condition, defined by a high-to-low transition on SDA

while SCK remains high. This indicates that an address/data

stream follows. All peripherals respond to the start condition

and shift the next eight bits (the 7-bit address and the R/W bit).

The bits are transferred from MSB to LSB. The peripheral that

recognizes the transmitted address responds by pulling the data

line low during the ninth clock pulse. This is known as an acknowl-

edge bit. All other devices withdraw from the bus at this point

and maintain an idle condition. The idle condition is where the

device monitors the SDA and SCK lines waiting for the start

condition and correct transmitted address. The R/W bit deter-

mines the direction of the data. Logic 0 on the LSB of the first

byte means that the master writes information to the peripheral.

Logic 1 on the LSB of the first byte means that the master reads

information from the peripheral.

The ADN2805 acts as a standard slave device on the bus. The data

on the SDA pin is eight bits long, supporting the 7-bit addresses,

plus the R/W bit. The ADN2805 has eight subaddresses to enable

the user-accessible internal registers (see

through

). It, therefore, interprets the first byte as the device address

and the second byte as the starting subaddress. Auto-increment

mode is supported, allowing data to be read from or written to

the starting subaddress and each subsequent address without

manually addressing the subsequent subaddress. A data trans-

fer is always terminated by a stop condition. The user can also

access any unique subaddress register on a one-by-one basis

without updating all registers.

Table 7

Table

11

Stop and start conditions can be detected at any stage of the

data transfer. If these conditions assert out of sequence with

normal read and write operations, they cause an immediate

jump to the idle condition. During a given SCK high period,

the user should issue one start condition, one stop condition,

or a single stop condition followed by a single start condition.

If an invalid subaddress is issued by the user, the ADN2805

does not issue an acknowledge and returns to the idle condi-

tion. If the user exceeds the highest subaddress while reading

back in auto-increment mode, the highest subaddress register

contents continue to be output until the master device issues a

no-acknowledge. This indicates the end of a read. In a no-acknowl-

edge condition, the SDATA line is not pulled low on the ninth

pulse. See Figure 7 and Figure 8 for sample read and write data

transfers and Figure 9 for a more detailed timing diagram.