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ISL43210A Datasheet(PDF) 8 Page - Renesas Technology Corp
RENESAS [Renesas Technology Corp]
ISL43210A Datasheet(HTML) 8 Page - Renesas Technology Corp
/ 12 page
FN7876 Rev 0.00
Page 8 of 12
Jun 24, 2011
The ISL43210A bidirectional, single SPDT analog switch offers
precise switching capability from a single 2.7V to 15V supply
with low ON-resistance (11Ω) and high speed operation.
The device is especially well suited for 3D TV and 3D eyeware
equipment thanks to the high single supply operating voltage
(15V), low power consumption (27µW max), fast switching
= 17ns), and the tiny SOT-23
packaging. High frequency applications also benefit from the
wide bandwidth and the very high off isolation rejection.
Supply Sequencing and Overvoltage
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
that might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and GND (see
Figure 8). To prevent forward biasing these diodes, V+ must be
applied before any input signals, and input signal voltages
must remain between V+ and GND. If these conditions cannot
be guaranteed, then one of the following two protection
methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ resistor in
series with the input (see Figure 8). The resistor limits the input
current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
Adding a series resistor to the switch input defeats the purpose
of using a low r
switch, so two small signal diodes can be
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 8). These additional diodes
limit the analog signal from 1V below V+ to 1V above GND. The
low leakage current performance is unaffected by this
approach, but the switch resistance may increase, especially
at low supply voltages.
The ISL43210A construction is typical of most CMOS analog
switches, except that it has only two supply pins: V+ and GND.
V+ and GND drive the internal CMOS switches and set their
analog voltage limits. Unlike switches with a 13V absolute
maximum voltage, the ISL43210A 16.5V absolute maximum
supply voltage provides plenty of room for the 10% tolerance
of 15V supplies, as well as room for overshoot and noise
The minimum recommended supply voltage is 2.7V. It is
important to note that the input signal range, switching times,
and ON-resistance degrade at lower supply voltages. Refer to
the “Electrical Specification” tables beginning on page 3 and
“Typical Performance Curves” beginning on page 9 for details.
V+ and GND also power the internal logic and level shifter. The
level shifter converts the input logic levels to switch V+ and
GND signals to drive the analog switch gate terminals.
This device cannot be operated with bipolar supplies because
the input switching point becomes negative in this
This switch is TTL compatible (0.8V and 2.4V) over a supply
range of 3V to 11V (see Figure 15). At 12V the V
about 2.5V. This is still below the TTL guaranteed high output
minimum level of 2.8V, but noise margin is reduced. For best
results with a 12V supply, use a logic family the provides a V
greater than 3V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving the
digital input signals from GND to V+ with a fast transition time
minimizes power dissipation.
In 50Ω systems, signal response is reasonably flat even past
300MHz (see Figure 16). Figure 16 also illustrates that the
frequency response is very consistent over a wide V+ range,
and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed-
through from a switch’s input to its output. Off isolation is the
resistance to this feed-through. Figure 17 details the high off
isolation rejection provided by this part. At 10MHz, off isolation
is about 50dB in 50Ω systems, decreasing approximately
20dB per decade as frequency increases. Higher load
impedances decrease off isolation rejection due to the voltage
divider action of the switch OFF impedance and the load
Reverse ESD protection diodes are internally connected between
each analog-signal pin and both V+ and GND. One of these diodes
conducts if any analog signal exceeds V+ or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given signal
pin are identical and therefore fairly well balanced, they are
reverse biased differently. Each is biased by either V+ or GND and
the analog signal. This means their leakages will vary as the
signal varies. The difference in the two diode leakages to the V+
and GND pins constitutes the analog-signal-path leakage current.
All analog leakage current flows between each pin and one of the
supply terminals, not to the other switch terminal. This is why both
sides of a given switch can show leakage currents of the same or
opposite polarity. There is no connection between the analog
signal paths and V+ or GND.
FIGURE 8. OVERVOLTAGE PROTECTION
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