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ISL12059 Datasheet(PDF) 7 Page - Renesas Technology Corp

Part No. ISL12059
Description  Low Cost and Low Power I2C Bus Real Time Clock/Calendar Low Power and Low Cost RTC
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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ISL12059 Datasheet(HTML) 7 Page - Renesas Technology Corp

 
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ISL12059
FN6757 Rev 0.00
Page 7 of 11
Jun 15, 2009
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time base for
the RTC. Since the resonant frequency of a crystal is
temperature dependent, the RTC performance will also be
dependent upon temperature. The frequency deviation of the
crystal is a function of the turnover temperature of the crystal
from the crystal’s nominal frequency. For example, a ~20ppm
frequency deviation translates into an accuracy of ~1 minute
per month. These parameters are available from the crystal
manufacturer.
I2C Serial Interface
The ISL12059 has an I2C serial bus interface that provides
access to the real time clock registers, and control and status
registers. The I2C serial interface is compatible with other
industry I2C serial bus protocols using a bi-directional data
signal (SDA) and a clock signal (SCL).
Register Descriptions
The registers are accessible following a slave byte of “1101000x”
and reads or writes to addresses [00h:07h]. The defined
addresses and default values are described in Table 1.
REGISTER ACCESS
The contents of the registers can be modified by performing a
byte or a page write operation directly to any register address.
The address will wrap around from 07h to 00h.
The registers are divided into 2 sections. These are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (1 byte): Address 07h.
There are no addresses above 07h.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC registers, the read instruction
latches all clock registers into a buffer, so an update of the
clock does not change the time being read. A sequential read
will not result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition to end
the operation and free the bus. After a read or write instruction,
the address remains at the previous address +1 so the user
can execute a current address read and continue reading the
next register.
Real Time Clock Registers
Addresses [00h to 06h]
RTC REGISTERS (SC, MN, HR, DW, DT, MO, YR)
These registers depict BCD representations of the time. As
such, SC (Seconds, address 00h) and MN (Minutes, address
01h) range from 0 to 59, HR (Hour, address 02h) is in a 24-
hour mode with a range from 0 to 23, DW (Day of the Week,
address 03h) is 0 to 6, DT (Date, address 04h) is 1 to 31, MO
(Month, address 05h) is 1 to 12, and YR (Year, address 06h) is
0 to 99.
The DW register provides a Day of the Week status and uses
three bits DW2 to DW0 to represent the seven days of the week.
The counter advances in the cycle 1-2-3-4-5-6-7-1-2-…
The assignment of a numerical value to a specific day of the
week is arbitrary and may be decided by the system software
designer.
Bit D7 of SC register contain the crystal enable/disable bit (ST).
Setting ST to “1” will disable the crystal from oscillating and
stop the counting in RTC register for the device to enter into
power saving mode. The ST bit is set to “0” on power-up for
normal operation.
Bit D7 of MN register contain the Oscillator Fail Indicator bit
(OF). This bit is set to a “1” when there is no oscillation on X1
pin. The OSF bit can only be reset by having an oscillation on
X1 and a write operation to reset it.
Bits D6 and D7 of HR register (century/hours register) contain
the century enable bit (CEB) and the century bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0' to '1' or from
'1' to '0' at the turn of the century (depending upon its initial
state). If CEB is set to a '0', CB will not toggle.
TABLE 1. REGISTER MEMORY MAP
ADDR. SECTION
REG
NAME
BIT
REG
7
6
543210
RANGE DEFAULT
00h
RTC
SC
ST
SC22
SC21
SC20
SC13
SC12
SC11
SC10
0 to 59
00h
01h
MN
OF
MN22
MN21
MN20
MN13
MN12
MN11
MN10
0 to 59
80h
02h
HR
CEB
CB
HR21
HR20
HR13
HR12
HR11
HR10
0 to 23
00h
03h
DW
0
0
0
0
0
DW12
DW11
DW10
1 to 7
01h
04h
DT
0
0
DT21
DT20
DT13
DT12
DT11
DT10
1 to 31
01h
05h
MO
0
0
0
MO20
MO13
MO12
MO11
MO10
1 to 12
01h
06h
YR
YR23
YR22
YR21
YR20
YR13
YR12
YR11
YR10
0 to 99
00h
07h
Control
FT/OUT
OUT
FT
00000
PF
N/A
81h


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