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S5T8702X01-E0R0 Datasheet(PDF) 9 Page - Samsung semiconductor |
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S5T8702X01-E0R0 Datasheet(HTML) 9 Page - Samsung semiconductor |
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9 / 62 page  FEEX TM ALPHANUMERIC DECODER II S5T8702 9 PACKET COMMUNICATION INITIATED BY THE FLEX DECODER IC Refer to figure 7 on page 11. When the S5T8702 has a packet for the host to read, the following occurs: 1. The S5T8702 drives the READY READY pin low. 2. If the S5T8702 is not already selected, the host selects the S5T8702 by driving the SS SS pin low. 3. The host receives (and sends) a 32-bit packet. 4. The host de-selects the S5T8702 by driving the SS SS pin high (optional). D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 High-impedance State MISO MOSI SCK READY READY SS SS 2 1 3 4 Figure 7: Typical Multiple Packet Communications Initiated by the FLEX decoder IC When the host is reading a packet from the S5T8702, it must send a valid packet to the S5T8702. If the host has no data to send, it is suggested that the host send a Checksum Packet with all of the data bits set to 0 in order to avoid disabling the S5T8702. See "Checksum Packet" on page 15 for more details on enabling and disabling the S5T8702. The following figure illustrates that it is not necessary to de-select the S5T8702 between packets then the packets are initiated by the S5T8702. D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 High-impedance State MISO MOSI SCK READY READY SS SS Figure 8: Multiple Packet Communications Initiated by the FLEX decoder IC with No De-select |
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