DS_S5T8702 datasheet(6/62 Pages) SAMSUNG

Part #	DS_S5T8702

Description	FEEX ALPHANUMERIC DECODER II

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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6 / 62 page

S5T8702

FEEX

TM ALPHANUMERIC DECODER II

6

PIN DESCRIPTION

PIN NAME

TYPE

DESCRIPTION

Power

VDD

3,13

Power

VSS

7,29

Ground

LOBAT

10

I

Low battery detect input

Reset

RESET

24

I

Active low reset to the S5T8702.

External Symbol Input Signals

EXTS1

11

I

MSb of the symbol currently being decoded

EXTS0

12

I

LSb of the symbol currently being decoded

SPI Signals

SS

27

I

Slave Select for SPI communications

SCK

28

I

Serial Clock for SPI communications

MOSI

30

I

Data input for SPI communications

MISO

31

O

Three-state data output for SPI communications

READY

26

O

Driven low when the IC is ready for an SPI packet

Clock Signals

CLKOUT

32

O

38.4 kHz or 40kHz clock output(derived from oscillator)

SYMCLK

14

O

Recovered symbol clock

EXTAL

6

I

76.8 kHz or 160kHz crystal input or external input

XTAL

5

O

76.8 kHz or 160kHz clock output

OSCPD

2

I

Internal oscillator power down.

Connected to VSS when using internal oscillator.

Connected to VDD when using an external source.

Receiver Control Lines

S1 - S7

22,21,20,1

9,18,16,15

O

Seven three-state receiver control output

S0 / IFIN

23

O / I

S0 : Receiver control output when using external

demodulator

IFIN : Limited IF input when using internal demodulator

Test pins

TEST2, TEST3

4,8

I

IC manufacturing test mode pin.

Normally connected to VSS.

NC

1,9,17,25

O

IC manufacturing test mode on.

Normally connected to Vss. (Can be left unconnected.)

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DS_S5T8702 Datasheet(PDF) 6 Page - Samsung semiconductor

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