CY2283
PRELIMINARY
2
Pin Summary
Name
Pins
Description
VDDQ3
6, 14, 19, 30, 36, 48 3.3V Digital voltage supply
VDDCPU
42
CPU Digital voltage supply, 2.5V or 3.3V
AVDD
1
Analog voltage supply, 3.3V
VSS
3, 9, 16, 22, 27, 33,
39, 45
Ground
XTALIN[3]
4
Reference crystal input
XTALOUT[3]
5
Reference crystal feedback
SDRAM7/ PCI_STOP
28
SDRAM clock output. Also, active LOW control input to stop PCI clocks, enabled
when MODE is LOW.
SDRAM6/CPU_STOP
29
SDRAM clock output. Also, active LOW control input to stop CPU clocks, enabled
when MODE is LOW.
SDRAM5/ PWR_DWN
31
SDRAM clock output. Also, active LOW control input to power down device,
enabled when MODE is LOW.
SDRAM[0:4],[8:11]
38, 37, 35, 34, 32,
21, 20, 18, 17
SDRAM clock outputs
SEL0
26
CPU frequency select input, bit 0 (see table below)
SEL1
46
CPU frequency select input, bit 0 (see table below)
CPUCLK[0:3]
44, 43, 41, 40
CPU clock outputs
PCICLK[0:3]
8, 10, 11, 12
PCI clock outputs, at one-half the CPU frequency.
PCICLK_F
7
Free-running PCI clock output
AGP[0:1]
13, 15
AGP clock outputs
REF0
2
3.3V Reference clock output
USBCLK
47
USB Clock output
SDATA
23
Serial data input for serial configuration port
SCLK
24
Serial clock input for serial configuration port
MODE
25
Mode Select pin for enabling power management features
Note:
3.
For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
Function Table
SEL1
SEL0
CPU/PCI
Ratio
CPUCLK[0:3]
SDRAM[0:11]
PCICLK[0:3]
PCICLK_F
AGP[0:1]
REF0
USBCLK
0
0
2.5
83.33 MHz
33.33 MHz
66.66 MHz
14.318 MHz
48 MHz
0
1
2
66.67 MHz
33.33 MHz
66.66 MHz
14.318 MHz
48 MHz
1
0
3.0
100.0 MHz
33.33 MHz
66.66 MHz
14.318 MHz
48 MHz
1
1
2.5
75.0 MHz
30.0 MHz
60.0 MHz
14.318 MHz
48 MHz
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