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CY7C09159
CY7C09169
PRELIMINARY
5
Note:
4.
CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
Electrical Characteristics Over the Operating Range
Symbol
Parameter
CY7C09159
CY7C09169
Units
-6
-7
-12
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOH
Output HIGH Voltage (VCC=Min,
IOH=–4.0 mA)
2.4
2.4
2.4
V
VOL
Output LOW Voltage (VCC=Min,
IOH= +4.0 mA)
0.4
0.4
0.4
V
VIH
Input HIGH Voltage
2.2
2.2
2.2
V
VIL
Input LOW Voltage
0.8
0.8
0.8
V
IOZ
Output Leakage Current
−10
10
−10
10
−10
10
µA
ICC
Operating Current
(VCC=Max, IOUT=0 mA)
Outputs Disabled
Com’l.
250
450
235
420
195
300
mA
Indust.
260
445
225
375
mA
ISB1
Standby Current (Both
Ports TTL Level)[4] CEL &
CER ≥ VIH, f=fMAX
Com’l.
45
115
40
105
30
85
mA
Indust.
55
120
45
100
mA
ISB2
Standby Current (One Port
TTL Level)[4] CEL | CER ≥
VIH, f=fMAX
Com’l.
175
235
160
220
125
190
mA
Indust.
175
235
140
205
mA
ISB3
Standby Current (Both
Ports CMOS Level)[4] CEL
& CER ≥ VCC – 0.2V, f=0
Com’l.
0.05
0.25
0.05
0.25
0.05
0.25
mA
Indust.
0.05
0.25
0.05
0.25
mA
ISB4
Standby Current (One Port
CMOS Level)[4] CEL | CER
≥ V
IH, f=fMAX
Com’l.
160
200
145
185
110
150
mA
Indust.
160
200
125
165
mA
Capacitance
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
10
pF
COUT
Output Capacitance
10
pF
AC Test Loads
3.0V
GND
90%
90%
10%
3ns
3 ns
10%
ALL INPUT PULSES
(a) Normal Load (Load 1)
R1 = 893
Ω
5V
OUTPUT
R2 = 347
Ω
C= 30 pF
VTH =1.4V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 2)
R1 = 893
Ω
R2 = 347
Ω
5V
OUTPUT
C= 5 pF
RTH =250Ω
≤
≤
(Used for tCKLZ, tOLZ, & tOHZ
including scope and jig)