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ISL97677 Datasheet(PDF) 19 Page - Renesas Technology Corp |
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ISL97677 Datasheet(HTML) 19 Page - Renesas Technology Corp |
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19 / 24 page  ISL97677 FN6996 Rev.2.00 Page 19 of 24 Sep 13, 2017 PWM Brightness Control Register (0x00) The Brightness control resolution has 256 steps of PWM duty cycle adjustment. The bit assignment is shown in Tables 2A and 2B. All of the bits in this Brightness Control Register can be read or write. Step 0 corresponds to the minimum step where the current is less than 10µA. Steps 1 to 255 represent the linear steps between 0.39% and 100% duty cycle with approximately 0.39% duty cycle adjustment per step. • An SMBus Write Byte cycle to Register 0x00 sets the PWM brightness level only if the backlight controller is in SMBus mode (see Table 3 “Operating Modes selected by Device Control Register Bits 1 and 2”). • An SMBus Read Byte cycle to Register 0x00 returns the programmed PWM brightness level, regardless of the value of PWM_SEL. • An SMBus setting of 0xFF for Register 0x00 sets the backlight controller to the maximum brightness. • An SMBus setting of 0x00 for Register 0x00 sets the backlight controller to the minimum brightness output in which the LED current is guaranteed to be less than 10µA. • Default value for Register 0x00 is 0xFF. Device Control Register (0x01) This register has 2 bits that control the operating mode of the backlight controller and a single bit that controls the BL ON/OFF state. The remaining bits are reserved. The bit assignment is shown in Tables 2A and 2B. All other bits in the Device Control Register will read as low unless otherwise written. Bits 7 and 6 are not implemented and will always read low. The PWM_SEL bit determines whether the SMBus or PWMI input should drive the output brightness in terms of PWM dimming. When PWM_SEL bit is 1, the PWMI drives the output brightness regardless of what the PWM_MD is. When the PWM_SEL bit is 0, the PWM_MD bit selects the manner in which the PWM dimming is to be interpreted; when this bit is 1, the PWM dimming is based on the SMBus brightness setting. When this bit is 0, the PWM dimming reflects a percentage change in the current brightness programmed in the SMBus Register 0x00, i.e. DPST (Display Power Saving Technology) mode, as shown in Equation 6: Where: Cbt = Current brightness setting from SMBus Register 0x00 without influence from the PWMI PWMI = is the percent duty cycle of the PWMI TABLE 2B. DATA BIT DESCRIPTIONS ADDRESS REGISTER DATA BIT DESCRIPTIONS 0x00 PWM Brightness Control Register BRT[7..0] = 256 steps of DPWM duty cycle brightness control 0x01 Device Control Register PWM_MD = PWM mode select bit (1 = absolute brightness, 0 = % change), default = 0 PWM_SEL = Brightness control select bit (1 = control by PWMI, 0 = control by SMBus), default = 0 BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0 0x02 Fault/Status Register 2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK) 1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK) BL_STAT = BL status (1 = BL On, 0 = BL Off) OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK) THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK) FAULT = Fault occurred (Logic “OR” of all of the fault conditions) 0x03 Identification Register MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9) REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins) PWM_MD PWM_SEL MODE X1 PWMI Mode 10 SMBus Mode 0 0 SMBus and PWMI mode with DPST TABLE 3. OPERATING MODES SELECTED BY DEVICE CONTROL REGISTER BITS 1 AND 2 PWM_MD PWM_SEL MODE X 1 PWMI Mode 10 SMBus Mode 0 0 SMBus and PWMI Mode with DPST DPST Brightness Cbt PWMI = (EQ. 6) |
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