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ISL97649B Datasheet(PDF) 17 Page - Renesas Technology Corp |
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ISL97649B Datasheet(HTML) 17 Page - Renesas Technology Corp |
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17 / 20 page  ISL97649B FN7927 Rev 2.00 Page 17 of 20 June 27, 2013 Start-up Sequence When VIN rising exceeds UVLO, it takes 120µs to read the settings stored in the chip in order to activate the chip correctly. When VIN is above UVLO and EN is high, the boost converter starts up. The gate pulse modulator output VGHM is held low until VDPM is charged to 1.215V. The detailed power-on sequence is shown in Figure 21. EN AVDD VIN UVLO UVLO PANEL NORMAL OPERATION VGHM VGHM OUTPUT TIED TO VGH WHEN VIN FALLS TO UVLO TSS_AVDD CONTROLLED BY VSS VOFF VON VCOM VDIV RESET 1.280V CD2 1.217V 1.222V 1.215V VDPM GPM ENABLED WHEN BOTH 1) EN = HIGH AND 2) VDPM >1.215V FIGURE 21. ISL97649B DETAILED POWER-ON/POWER-OFF SEQUENCE |
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