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ASM5P2304AG-2H-08-ST Datasheet(PDF) 3 Page - Alliance Semiconductor Corporation |
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ASM5P2304AG-2H-08-ST Datasheet(HTML) 3 Page - Alliance Semiconductor Corporation |
3 / 15 page September 2005 ASM5P2304A rev 1.4 3.3V Zero Delay Buffer 3 of 15 Notice: The information in this document is subject to change without notice. Pin Configuration Pin Description for ASM5P2304A Pin # Pin Name Description 1 REF 1 Input reference frequency, 5V tolerant input 2 CLKA1 2 Buffered clock output, bank A 3 CLKA2 2 Buffered clock output, bank A 4 GND Ground 5 CLKB1 2 Buffered clock output, bank B 6 CLKB2 2 Buffered clock output, bank B 7 VDD 3.3V supply 8 FBK PLL feedback input Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. ASM5P2304A 5 6 7 8 FBK VDD CLKB2 CLKB1 4 3 2 1 GND CLKA1 REF CLKA2 |
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