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ASM5P2304AG-2-08-SR Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
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ASM5P2304AG-2-08-SR Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
2 / 15 page September 2005 ASM5P2304A rev 1.4 3.3V Zero Delay Buffer 2 of 15 Notice: The information in this document is subject to change without notice. ASM5P2304A Configurations Device Feedback From Bank A Frequency Bank B Frequency ASM5P2304A-1 Bank A or Bank B Reference Reference ASM5P2304A-1H Bank A or Bank B Reference Reference ASM5P2304A-2 Bank A Reference Reference /2 ASM5P2304A-2 Bank B 2 X Reference Reference ASM5P2304A-2H Bank A Reference Reference/2 ASM5P2304A-2H Bank B 2 X Reference Reference Zero Delay and Skew Control For applications requiring zero input-output delay, all outputs must be equally loaded . To close the feedback loop of the ASM5P2304A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 0 -500 -1000 -1500 500 1000 1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins |
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