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ISL85012 Datasheet(PDF) 17 Page - Renesas Technology Corp
RENESAS [Renesas Technology Corp]
ISL85012 Datasheet(HTML) 17 Page - Renesas Technology Corp
/ 19 page
Page 17 of 19
Mar 17, 2017
The layout is very important in high frequency switching
converter design. With power devices switching efficiently at
600kHz, the resulting current transitions from one device to
another causing voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage spikes
can degrade efficiency, radiate noise into the circuit and lead to
device overvoltage stress. Careful component layout and printed
circuit board design minimizes these voltage spikes.
As an example, consider the turn-off transition of the upper
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET and
is picked up by the internal body diode of the low-side MOSFET.
Any parasitic inductance in the switched current path generates
a large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components, and
short, wide traces minimize the magnitude of voltage spikes.
A multilayer printed circuit board is recommended. Figures 40
and 41 show the recommended layout of the top layer and the
inner Layer 1 of the schematic in Figure 1 on page 1.
1. Place the input ceramic capacitors between PVIN and GND
pins. Put them as close to the pins as possible.
2. A 1µF decoupling input ceramic capacitor is recommended.
Place it as close to the VIN pin as possible.
3. A 2.2µF decoupling ceramic capacitor is recommended for
VDD pin. Place it as close to the VDD pin as possible.
4. The entire inner Layer 1 is recommended to be the GND plane
in order to reduce the noise coupling.
5. The switching node (PHASE) plane needs to be kept away
from the feedback network. Place the resistor divider close to
6. Put three to five vias on the GND pin to connect the GND plane
of other layers for better thermal performance. This allows the
heat to move away from the IC. Keep the vias small but not so
small that their inside diameter prevents solder wicking
through the holes during reflow. An 8 mil hole with 15 mil
diameter vias are used on the evaluation board. Do not use
“thermal relief” patterns to connect the vias. It is important to
have a complete connection of the plated-through hole to
FIGURE 40. RECOMMENDED TOP LAYER LAYOUT
FIGURE 41. SOLID GND PLANE OF INNER LAYER 1
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