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ISL85012 Datasheet(PDF) 15 Page  Renesas Technology Corp 

ISL85012 Datasheet(HTML) 15 Page  Renesas Technology Corp 
15 / 19 page ISL85012 FN8677 Rev.2.00 Page 15 of 19 Mar 17, 2017 One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL85012 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. Equations 11 and 12 give the approximate response time interval for application and removal of a transient load: where ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection Use a mix of input bypass capacitors to control the input voltage ripple. Use ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the switching MOSFET turns on. Place the ceramic capacitors physically close to the MOSFET VIN pins (switching MOSFET drain) and PGND. The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. For most cases, the RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. The maximum RMS current required by the regulator may be closely approximated through Equation 13: For a throughhole design, several electrolytic capacitors may be needed, especially at temperatures less than 25°C. The electrolytic's ESR can increase ten times higher than at room temperature and cause input line oscillation. In this case, a more thermally stable capacitor such as X7R ceramic should be used. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. Some capacitor series available from reputable manufacturers are surge current tested. Loop Compensation Design When COMP is not connected to GND through a 200Ω resistor, the COMP pin is active for external loop compensation. The regulator uses constant frequency peak current mode control architecture to achieve a fast loop transient response. An accurate current sensing pilot device in parallel with the highside switch is used for peak current control signal and overcurrent protection. The inductor is not considered as a state variable since its peak current is constant, and the system becomes a single order system. It is much easier to design a type II compensator to stabilize the loop than to implement voltage mode control. Peak current mode control has an inherent input voltage feedforward function to achieve good line regulation. Figure 35 shows the small signal model of the synchronous buck regulator. To simplify the analysis, sample and hold effect block He(s) and slope compensation are not taken into account. Assume Vcomp is equal to the current sense signal ILxRt and ignore the DCR of the inductor, the power train can be approximated by a voltage controlled current source supplying current to the output capacitor and load resistor (see Figure 36). The transfer function frequency response is presented in Figure 37. tRISE = L x ITRAN VIN  VOUT (EQ. 11) (EQ. 12) tFALL = L x ITRAN VOUT IRMS MAX VOUT VIN  IOUT MAX 2 1 12  VIN VOUT – LfSW  VOUT VIN  2 + = (EQ. 13) FIGURE 35. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR 1:D ILd VIN VINd Rt He(s) Av(s) Fm L Rc Co Ro DCR d Ti(s) Vcomp Tv(s) IL Vo FIGURE 36. POWER TRAIN SMALL SIGNAL MODEL L Rc Co Vo Vcomp IL 1/Rt Ro 
