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ISL85012 Datasheet(PDF) 14 Page  Renesas Technology Corp 

ISL85012 Datasheet(HTML) 14 Page  Renesas Technology Corp 
14 / 19 page ISL85012 FN8677 Rev.2.00 Page 14 of 19 Mar 17, 2017 High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. The shape of the output voltage waveform during a load transient that represents the worst case loading conditions, will ultimately determine the number of output capacitors and their type. When this load transient is applied to the converter, most of the energy required by the load is initially delivered from the output capacitors. This is due to the finite amount of time required for the inductor current to slew up to the level of the output current required by the load. This phenomenon results in a temporary dip in the output voltage. At the very edge of the transient, the Equivalent Series Inductance (ESL) of each capacitor induces a spike that adds on top of the existing voltage drop due to the Equivalent Series Resistance (ESR). After the initial spike, attributable to the ESR and ESL of the capacitors, the output voltage experiences sag. This sag is a direct consequence of the amount of capacitance on the output. During the removal of the same output load, the energy stored in the inductor is dumped into the output capacitors. This energy dumping creates a temporary hump in the output voltage. This hump, as with the sag, can be attributed to the total amount of capacitance on the output. Figure 34 shows a typical response to a load transient. The amplitudes of the different types of voltage excursions can be approximated using Equations 3, 4, 5 and 6. where ITRAN = Output Load Current Transient and COUT = Total Output Capacitance. In a typical converter design, the ESR of the output capacitor bank dominates the transient response. The ESR and the ESL are typically the major contributing factors in determining the output capacitance. The number of output capacitors can be determined by using Equation 7, which relates the ESR and ESL of the capacitors to the transient load step and the tolerable output voltage excursion during load transient ( Vo): If VSAG and/or VHUMP are found to be too large for the output voltage limits, then the amount of capacitance may need to be increased. In this situation, a tradeoff between output inductance and output capacitance may be necessary. The ESL of the capacitors, which is an important parameter in the previous equations, is not usually listed in specification. Practically, it can be approximated using Equation 8 if an Impedance vs Frequency curve is given for a specific capacitor: where fres is the frequency where the lowest impedance is achieved (resonant frequency). The ESL of the capacitors becomes a concern when designing circuits that supply power to loads with high rates of change in the current. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by Equations 9 and 10: Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. It is recommended to set the ripple inductor current to approximately 30% of the maximum output current for optimized performance. Recommend the design of the inductor ripple current does not exceeds 5A in the applications of ISL85012. FIGURE 34. TYPICAL TRANSIENT RESPONSE DVESL DVESR DVSAG DVHUMP Itran VOUT IOUT (EQ. 3) V ESR ESR ITRAN = V ESL ESL ITRAN dt  = (EQ. 4) (EQ. 5) V SAG Lout ITRAN 2 2COUT VIN VOUT –  = (EQ. 6) V HUMP Lout ITRAN 2 2COUT VOUT  = Number of Capacitors ESL ITRAN dt  ESR ITRAN + V o  = (EQ. 7) ESL 1 C2 fres 2  = (EQ. 8) (EQ. 9) I VIN VOUT – fSW L  VOUT VIN  = (EQ. 10) V OUT IESR = 
